Publication Details
Metodika návrhu řadiče rekonfigurace pro Systémy odolné proti poruchám
Reconfiguration Controller, Fault Tolerant Systems, Partial Reconfiguration, FPGA.
Field Programmable Gate Arrays (FPGAs) are nowadays popular not only for embedded systems. Their disadvantage is the susceptibility to solar activity which causes configuration memory faults due to radiation known as SEU. These can cause system failure. Therefore, a number of methods are being developed to increase the fault tolerance. The spatial redundancy is typical used for FPGA, eg TMR, which masks faults only. Therefore, it is very appropriate to use the key capabilities of the FPGA - reconfiguration which is able to repair faults. Everything needed to be reconfigured must be secured by the controller. However, there are many approaches to implementing it and therefore I deal with its proposal in the dissertation. In addition, a tool for estimating the reliability of a TMR based system and reconfiguration is presented. The tool is based on a system simulation with MTTF parameters and reconfiguration time.
@inproceedings{BUT155072,
author="Richard {Pánek}",
title="Metodika návrhu řadiče rekonfigurace pro Systémy odolné proti poruchám",
booktitle="Počítačové architektury & diagnostika 2018",
year="2018",
pages="21--24",
publisher="Západočeská univerzita v Plzni",
address="Stachy",
isbn="978-80-261-0814-6",
url="https://www.fit.vut.cz/research/publication/11770/"
}