Publication Details

Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture

KUTÁLEK, V.; DVOŘÁK, V. Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and System Workshop. Brno: Faculty of Information Technology BUT, 2002. p. 296-299. ISBN: 80-214-2094-4.

Czech title

Simulace a prototypování multiprocesorových SoC na zřetězené procesorové architektuře

Type

conference paper

Language

English

Authors

Kutálek Vladimír, Ing., Ph.D.
Dvořák Václav, prof. Ing., DrSc.

Keywords

Multiprocessor SoC, pipeline/farm architecture, performance prediction

Abstract

Process- and thread-level parallelism is very often exploited inasynchronous processor pipelines for embedded applications, recently ona chip. The paper deals with simulation of pipelines with one or moreworkers in each pipeline stage. The number of workers can be adjustedto balance execution time of other stages so as to keep efficiencyhigh. Simulation-based prototyping of such pipeline processor farmsusing Transim tool can account for communication delays, multitasking,data-dependent variations in workload, CPUs with different speeds, etc.Simulation results for a given task divisible to a few subtasks ofarbitrary duration are presented as well as a particular example of apower of a matrix.

Published

2002

Pages

296–299

Proceedings

Proceedings of IEEE Design and Diagnostics of Electronic Circuits and System Workshop

ISBN

80-214-2094-4

Publisher

Faculty of Information Technology BUT

Place

Brno

BibTeX

@inproceedings{BUT9823,
  author="Vladimír {Kutálek} and Václav {Dvořák}",
  title="Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture",
  booktitle="Proceedings of IEEE Design and Diagnostics of Electronic Circuits and System Workshop",
  year="2002",
  pages="296--299",
  publisher="Faculty of Information Technology BUT",
  address="Brno",
  isbn="80-214-2094-4"
}