Publication Details

Low-Latency Modular Packet Header Parser for FPGA

KEKELY, L.; PUŠ, V.; KOŘENEK, J. Low-Latency Modular Packet Header Parser for FPGA. ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Austin: Association for Computing Machinery, 2012. p. 77-78. ISBN: 978-1-4503-1685-9.
Czech title
Nízko-latentní modulární analyzátor hlaviček paketov pro FPGA
Type
conference paper
Language
English
Authors
Kekely Lukáš, Ing., Ph.D. (DCSY)
Puš Viktor, Ing., Ph.D.
Kořenek Jan, doc. Ing., Ph.D. (DCSY)
Keywords

Packet Parsing, Latency, FPGA

Abstract

Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application. The parser is handoptimized thanks to the direct implementation in VHDL, yet the structure is very uniform and easily extensible for new protocols.

Published
2012
Pages
77–78
Proceedings
ACM/IEEE Symposium on Architectures for Networking and Communications Systems
ISBN
978-1-4503-1685-9
Publisher
Association for Computing Machinery
Place
Austin
BibTeX 
@inproceedings{BUT97063,
  author="Lukáš {Kekely} and Viktor {Puš} and Jan {Kořenek}",
  title="Low-Latency Modular Packet Header Parser for FPGA",
  booktitle="ACM/IEEE Symposium on Architectures for Networking and Communications Systems",
  year="2012",
  pages="77--78",
  publisher="Association for Computing Machinery",
  address="Austin",
  isbn="978-1-4503-1685-9",
  url="https://www.fit.vut.cz/research/publication/10197/"
}
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