Publication Details
A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems
Salvador Ruben (RG EHW)
Mora Javier
De la Torre Eduardo
Riesgo Teresa
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
field programmable gate array, adaptive hardware, dynamic partial reconfiguration, IP core, evolvable hardware
Modern FPGAs with Dynamic and Partial Reconfiguration (DPR) features allow the implementation of complex, yet flexible, hardware systems. Combining this flexibility with evolvable hardware techniques, real adaptive systems, able to reconfigure themselves according to environmental changes, can be envisaged. In this paper, a highly regular and modular architecture combined with a fast reconfiguration mechanism is proposed, allowing the introduction of dynamic and partial reconfiguration in the evolvable hardware loop. Results and use case show that, following this approach, evolvable processing IP Cores can be built, providing intensive data processing capabilities, improving data and delay overheads with respect to previous proposals. Results also show that, in the worst case (maximum mutation rate), average reconfiguration time is 5 times lower than evaluation time.
@inproceedings{BUT76399,
author="Andres {Otero} and Ruben {Salvador} and Javier {Mora} and Eduardo {De la Torre} and Teresa {Riesgo} and Lukáš {Sekanina}",
title="A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems",
booktitle="Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems",
year="2011",
pages="336--343",
publisher="IEEE Computer Society",
address="Los Alamitos",
isbn="978-1-4577-0599-1"
}