Publication Details

Decreasing Test Time by Scan Chain Reorganization

BARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J. Decreasing Test Time by Scan Chain Reorganization. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 371-374. ISBN: 978-1-4244-9753-9.
Czech title
Zkracování doby aplikace testu přeuspořádáním scan řetězce
Type
conference paper
Language
English
Authors
Bartoš Pavel, Ing.
Kotásek Zdeněk, doc. Ing., CSc.
Dohnal Jan
Keywords

scan chain, test, time, reordering, reorganization, physical, layout

Abstract

In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.

Published
2011
Pages
371–374
Proceedings
IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
ISBN
978-1-4244-9753-9
Publisher
IEEE Computer Society
Place
Cottbus
BibTeX 
@inproceedings{BUT76306,
  author="Pavel {Bartoš} and Zdeněk {Kotásek} and Jan {Dohnal}",
  title="Decreasing Test Time by Scan Chain Reorganization",
  booktitle="IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
  year="2011",
  pages="371--374",
  publisher="IEEE Computer Society",
  address="Cottbus",
  isbn="978-1-4244-9753-9"
}
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