Publication Details
Two Level Testability System
Růžička Richard, doc. Ing., Ph.D., MBA (DCSY)
Strnadel Josef, Ing., Ph.D. (DCSY)
Zbořil František, doc. Ing., CSc. (DITS)
RTL, Testability Analysis, VHDL
Principles of two level testability analysis system are described in the paper.
The behavioural description of the unit under analysis (UUA) is the first level,
on which the source VHDL file is taken as an input. On this level, the VHDL
constructions which might cause testability problems in the resulting design are
identified and the possibility of deriving i paths is evaluated. The RT level is
the second level, on which the testability aspects are taken into account. For
these purposes, the RT level structure is converted into a directed labelled
graph which reflects the structure of the UUA and its diagnostic features which
are important for the testability analysis. The analysis is done on the graph
instead of on the VHDL source text.
The paper deals with principles of two level testability analysis system. The source VHDL file is taken as an input. The RT level structure is converted into a directed labelled graph. The analysis is done on the graph instead of on the VHDL source text.
@inproceedings{BUT5604,
author="Zdeněk {Kotásek} and Richard {Růžička} and Josef {Strnadel} and František {Zbořil}",
title="Two Level Testability System",
booktitle="Proceedings of the 35th Spring International Conference MOSIS'01",
year="2001",
pages="433--440",
address="Ostrava",
isbn="80-85988-57-7"
}