Publication Details
An Evolvable Combinational Unit for FPGAs
Friedl Štěpán, Ing.
combinational circuit, evolutionary design, evolvable hardware, field programmable gate array
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables.
@article{BUT46258,
author="Lukáš {Sekanina} and Štěpán {Friedl}",
title="An Evolvable Combinational Unit for FPGAs",
journal="Computing and Informatics",
year="2004",
volume="23",
number="5",
pages="461--486",
issn="1335-9150",
url="http://www.fit.vutbr.cz/~sekanina/publ/cai/cai04.pdf"
}