Publication Details
Evolutionary Functional Recovery in Virtual Reconfigurable Circuits
hardware, logic design, reliability, reconfigurable circuit, evolutionary
algorithm
A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device
developed using an ordinary FPGA in order to easily implement evolvable hardware
applications. While a fast partial run-time reconfiguration and
application-specific programmable elements represent the main advantages of VRC,
the main disadvantage of the VRC is the area consumed. This study describes
experiments conducted to estimate how the use of VRC influences the dependability
of FPGA-based evolvable systems. It is shown that these systems are not as
sensitive to faults as their area-demanding implementations might suggest. An
evolutionary algorithm is utilized to design fault tolerant circuits as well as
to perform an automatic functional recovery when faults are detected in the
configuration memory of the FPGA. All the experiments are performed on models of
reconfigurable devices.
@article{BUT45162,
author="Lukáš {Sekanina}",
title="Evolutionary Functional Recovery in Virtual Reconfigurable Circuits",
journal="ACM Journal on Emerging Technologies in Computing Systems",
year="2007",
volume="3",
number="2",
pages="1--22",
issn="1550-4832",
url="http://www.fit.vutbr.cz/~sekanina/publ/ject/ject07.pdf"
}