Publication Details

An Evolvable Hardware System in Xilinx Virtex II Pro FPGA

VAŠÍČEK, Z.; SEKANINA, L. An Evolvable Hardware System in Xilinx Virtex II Pro FPGA. International Journal of Innovative Computing and Applications, 2007, vol. 1, no. 1, p. 63-73. ISSN: 1751-648X.
Czech title
An Evolvable Hardware System in Xilinx Virtex II Pro FPGA
Type
journal article
Language
English
Authors
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
URL
Keywords

image filter, evolvable hardware, FPGA

Abstract

In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average.  

Published
2007
Pages
63–73
Journal
International Journal of Innovative Computing and Applications, vol. 1, no. 1, ISSN 1751-648X
DOI
10.1504/IJICA.2007.013402
EID Scopus
2-s2.0-34547519629
BibTeX 
@article{BUT45160,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="An Evolvable Hardware System in Xilinx Virtex II Pro FPGA",
  journal="International Journal of Innovative Computing and Applications",
  year="2007",
  volume="1",
  number="1",
  pages="63--73",
  doi="10.1504/IJICA.2007.013402",
  issn="1751-648X",
  url="http://dx.doi.org/10.1504/IJICA.2007.013402"
}
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