Publication Details
Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences
test vector, scan chain, low power, power dissipation, optimization, genetic
algorithm, CMOS, AMI, ordering
In the paper, novel method for reducing power dissipation during test application
time is presented. When compared to existing methods, its advantage can be seen
in the fact that power dissipation is evaluated by means of precise and fast
simulation based metric rather than by means of commonly utilized simple metric
based on evaluating Hamming distance between test vectors. In our method, the
metric is evaluated over CMOS primitives from AMI technological libraries. In
order to reduce power dissipation, the sequence of test vectors to be applied and
proper ordering of registers within scan chains are optimized. In existing
approaches, the optimizations are typically performed separately in a sequence
because problems they correspond to are seen to be independent. On contrary to
that, we have united the search spaces and solved these two problems as a single
optimization task. Genetic algorithm operating over an appropriate encoding of
the problem was utilized to optimize the problem. Proposed method was implemented
in both single and multiprocessor environments and it was successfully tested to
cooperate with commercial tools. At the end of the paper, results achieved over
benchmarks from ISCAS85, ISCAS89 and ITC99 sets are presented and compared to
results of existing methods.
@inproceedings{BUT35979,
author="Zdeněk {Kotásek} and Jaroslav {Škarvada} and Josef {Strnadel}",
title="Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences",
booktitle="Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
year="2010",
pages="364--369",
publisher="IEEE Computer Society",
address="Vienna",
isbn="978-1-4244-6610-8",
url="https://www.fit.vut.cz/research/publication/9201/"
}