Publication Details
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption
test vector, scan chain, low power, power consumption, optimization, genetic
algorithm, CMOS, AMI, ordering, correlation
In most of existing approaches, the reorganization of test vector sequence and
reordering scan chains registers to reduce power consumption are solved
separately, they are seen as independent procedures. In the paper it is shown
that a correlation between these two processes and strong reasons to combine
them into one procedure run concurrently exist. Based on this idea, it is
demonstrated that search spaces of both procedures can be combined together into
a single search space in order to achieve better results during the optimization
process. The optimization over the united search space was tested on ISCAS85,
ISCAS89 and ITC99 benchmark circuits implemented by means of CMOS primitives from
AMI technological libraries. Results presented in the paper show that lower power
consumption can be achieved if the correlation is reflected, i.e., if the search
space is united rather than divided into separate spaces. At the end of the
paper, results achieved by genetic algorithm based optimization are presented,
discussed and compared with results of existing methods.
@inproceedings{BUT35934,
author="Zdeněk {Kotásek} and Jaroslav {Škarvada} and Josef {Strnadel}",
title="The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption",
booktitle="Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools",
year="2010",
pages="644--651",
publisher="IEEE Computer Society",
address="Los Alamitos",
isbn="978-0-7695-4171-6",
url="https://www.fit.vut.cz/research/publication/9342/"
}