Publication Details
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application
test application, power consumption, reduction, optimization, genetic algorithm, scan chain, scan register, test vector, reordering, benchmark, digital circuit
In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues are the ordering of test vectors and scan registers with the goal of reducing switching activity during test application and power consumption as a consequence of the ordering. The principles of developing an optimizing procedure with the aim of achieving a solution satisfying the required value of power consumption during power consumption are described here. A basic description of the methodology together with the functions needed to implement the procedures is provided. Experimental results are also discussed.
@inproceedings{BUT35933,
author="Jaroslav {Škarvada} and Zdeněk {Kotásek} and Josef {Strnadel}",
title="The Use of Genetic Algorithm to Reduce Power Consumption during Test Application",
booktitle="Evolvable Systems: From Biology to Hardware",
year="2010",
series="Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 6274",
journal="Lecture Notes in Computer Science",
volume="2010",
number="6274",
pages="181--192",
publisher="Springer Verlag",
address="Berlin",
doi="10.1007/978-3-642-15323-5\{_}16",
isbn="978-3-642-15322-8",
issn="0302-9743",
url="https://www.fit.vut.cz/research/publication/9341/"
}