Fast Cycle-Accurate Interpreted Simulation

Thearea of hardware/software co-design deals with the design of ASIPs(Application Specific Instruction-setProcessors) because they often create the core of an embedded system.Embedded systems with ASIPs are designed for a given task and theyhave to fulfill several criteria, such as power consumption, chip size,etc. The success of the design phase is closely related to theexistence of good design tools, i.e. tools for ASIP programming andsimulation. The simulation itself is very important, because with itwe can verify and validate an ASIP design. For this purpose, ASIPsare described using an architecture description language that allowsgenerating the design tools in an automatic way. In this article, wefocus on presenting the principles which are used in our fastcycle-accurate interpreted simulator. Beside the simulation speed, wealso focus on equivalence assurance between an ASIP simulator and itshardware realization.