Publication Details

Checker Design for On-line Testing of Xilinx FPGA Communication

STRAKA, M.; TOBOLA, J.; KOTÁSEK, Z. Checker Design for On-line Testing of Xilinx FPGA Communication. In The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Rome: IEEE Computer Society, 2007. p. 152-160. ISBN: 0-7695-2885-6.

Czech title

Type

conference paper

Language

English

Authors

Straka Martin, Ing., Ph.D.
Tobola Jiří, Ing., MBA (FIT IB)
Kotásek Zdeněk, doc. Ing., CSc.

Keywords

Communication Protocol Testing, Fault Tolerant Systems, checker design

Abstract

In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.

Published

2007

Pages

152–160

Proceedings

The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

ISBN

0-7695-2885-6

Publisher

IEEE Computer Society

Place

Rome

BibTeX

@inproceedings{BUT28609,
  author="Martin {Straka} and Jiří {Tobola} and Zdeněk {Kotásek}",
  title="Checker Design for On-line Testing of Xilinx FPGA Communication",
  booktitle="The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",
  year="2007",
  pages="152--160",
  publisher="IEEE Computer Society",
  address="Rome",
  isbn="0-7695-2885-6"
}