Publication Details

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

SEKANINA, L. Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates. 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Gliwice: IEEE Computer Society, 2007. p. 243-246. ISBN: 1424411610.

Czech title

Type

conference paper

Language

English

Authors

Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)

URL

http://www.fit.vutbr.cz/~sekanina/publ/ddecs07/ddecs07.pdf

Keywords

digital circuit, polymorphic gate, adder, testing

Abstract

TBD

Published

2007

Pages

243–246

Proceedings

2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

ISBN

1424411610

Publisher

IEEE Computer Society

Place

Gliwice

BibTeX

@inproceedings{BUT28586,
  author="Lukáš {Sekanina}",
  title="Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates",
  booktitle="2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2007",
  pages="243--246",
  publisher="IEEE Computer Society",
  address="Gliwice",
  isbn="1424411610",
  url="http://www.fit.vutbr.cz/~sekanina/publ/ddecs07/ddecs07.pdf"
}