Publication Details

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

STAREČEK, L.; SEKANINA, L.; KOTÁSEK, Z. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008. p. 255-258. ISBN: 978-1-4244-2276-0.
Czech title
Redukce počtu testovacích vektorů pomocí rekonfigurace na úrovni hradel
Type
conference paper
Language
English
Authors
Stareček Lukáš, Ing., Ph.D. (RG EHW)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Kotásek Zdeněk, doc. Ing., CSc.
Keywords

digital circuit, test vector, reconfiguration

Abstract

In this paper, a new concept which allows the reduction of test vectors volume is presented. The concept is based on reconfiguration of some gates of circuit under test. Instead of testing the original circuit, a circuit which has the same topology (but some of its gate functions are reconfigured) is actually tested. Two possible implementations of the reconfiguration are investigated. Preliminary experiments indicate that test length can be reduced to approx. 70% of its initial value while the increase in transistors is moderate.

Published
2008
Pages
255–258
Proceedings
Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
ISBN
978-1-4244-2276-0
Publisher
IEEE Computer Society
Place
Bratislava
BibTeX 
@inproceedings{BUT27766,
  author="Lukáš {Stareček} and Lukáš {Sekanina} and Zdeněk {Kotásek}",
  title="Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration",
  booktitle="Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop",
  year="2008",
  pages="255--258",
  publisher="IEEE Computer Society",
  address="Bratislava",
  isbn="978-1-4244-2276-0",
  url="https://www.fit.vut.cz/research/publication/8603/"
}
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