Publication Details
Automatizované mapování architektur s proměnným počtem výpočetních elementů
High-Level Sythesis, Design Space Exploration, FPGA technology, Approximate String Matching.
Architectures of digital circuits are usually composed of repetitive elements in form of computation units or memory blocks. These elements are usuallt organized to n-dimensional arrays or tree structures. The process of automated mapping of such architectures into the chips with limited amount of resources is complicated by several factors. To the most important ones belong: computation of architecture dimensions, selection of type of resources for element individual parts. This paper describes the basic framework of such method for automated mapping of architectures composed of variable number of processing elements. Proposed method is evaluated on example of circuit for approximate string matching using Smith-Waterman algorithm and achieved results are compared with others approaches in this area.
@inproceedings{BUT26074,
author="Tomáš {Martínek}",
title="Automatizované mapování architektur s proměnným počtem výpočetních elementů",
booktitle="Počítačové architektury a diagnostika 2007. Česko-slovenský seminář pro studenty doktorandského studia",
year="2007",
pages="77--83",
publisher="Západočeská univerzita v Plzni",
address="Plzeň",
isbn="978-80-7043-605-9"
}