Automatic Generation of Circuits for Approximate String Matching

automated design, approximate string matching, generic systolic array architecture, FPGA

Hardware accelerators for approximate string matching  play an important role in an increasing number of modern bioinformatic applications. They are able to reduce the task complexity from quadratic to linear and show a speed up in orders of hundreds when compared with the respective software implementation. However, their wider use is limited by the lack of flexibility and modularity required by often variable tasks. In this respect, it is desirable to develop a procedure for automatic design and implementation of such accelerators, to reach high performance and efficiency typical for strongly optimized architectures, with as little human effort on the side of the designer as possible. This paper proposes the essential element of such a procedure, a method for the calculation of generic hardware architecture parameters. The proposed method is evaluated on a range of typical approximate string matching tasks. It demonstrates the differences in the designed architecture, when performance of individual tasks is maximized.