Publication Details

Verifying VHDL Design with Multiple Clocks in SMV

SMRČKA, A.; ŘEHÁK, V.; VOJNAR, T.; ŠAFRÁNEK, D.; MATOUŠEK, P.; ŘEHÁK, Z. Verifying VHDL Design with Multiple Clocks in SMV. Proceedings of FMICS 2006. Bonn: 2006. p. 140-155.
Czech title
Verifying VHDL Design with Multiple Clocks in SMV
Type
conference proceedings
Language
English
Authors
Smrčka Aleš, Ing., Ph.D. (DITS)
Řehák Vojtěch, doc. RNDr.
Vojnar Tomáš, prof. Ing., Ph.D. (DITS)
Šafránek David
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS)
Řehák Zdeněk
URL
Keywords

model checking, hardware, VHDL, multiple clocks, SMV

Abstract

The paper considers the problem of model checking real-life VHDL-based hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, ie. designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project.

Published
2006
Pages
140–155
Book
Proceedings of FMICS 2006
Place
Bonn
BibTeX 
@proceedings{BUT22281,
  editor="Aleš {Smrčka} and Vojtěch {Řehák} and Tomáš {Vojnar} and David {Šafránek} and Petr {Matoušek} and Zdeněk {Řehák}",
  title="Verifying VHDL Design with Multiple Clocks in SMV",
  year="2006",
  pages="140--155",
  address="Bonn"
}
Back to top