Publication Details

On Distribution of Testability Values in Scan-Layout State-Space

STRNADEL, J. On Distribution of Testability Values in Scan-Layout State-Space. Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics. Košice: The University of Technology Košice, 2006. p. 308-313. ISBN: 80-8073-598-0.
Czech title
Rozložení hodnot testovatelnosti ve stavovém prostoru konfigurací scan řetězů
Type
conference paper
Language
English
Authors
Strnadel Josef, Ing., Ph.D. (DCSY)
Keywords

digital circuit diagnostics, register-transfer level, circuit data-path, testability analysis, design for testability, testability improvements, scan technique

Abstract

In the paper, it is shown how are testability values distributed within the scan-layout state-space for particular digital circuit. The goal of the paper was to approve or dismiss our hypothesis that the more registers are included in greater number of multiple scan-chains within particular scan-layout, the better testability properties correspond to the scan-layout.

Published
2006
Pages
308–313
Proceedings
Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics
ISBN
80-8073-598-0
Publisher
The University of Technology Košice
Place
Košice
BibTeX 
@inproceedings{BUT22271,
  author="Josef {Strnadel}",
  title="On Distribution of Testability Values in Scan-Layout State-Space",
  booktitle="Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics",
  year="2006",
  pages="308--313",
  publisher="The University of Technology Košice",
  address="Košice",
  isbn="80-8073-598-0",
  url="https://www.fit.vut.cz/research/publication/8181/"
}
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