Publication Details

REUSE OF FORMAL SPECIFICATIONS IN EMBEDDED SYSTEMS DESIGN

ŠVÉDA, M. REUSE OF FORMAL SPECIFICATIONS IN EMBEDDED SYSTEMS DESIGN. In Proceedings of IFAC Workshop on PROGRAMMABLE DEVICES and EMBEDDED SYSTEMS PDeS 2006. Brno: Faculty of Electrical Engineering and Communication BUT, 2006. p. 78-83. ISBN: 80-214-3130-X.

Czech title

Opakovaná využitelnost formálních specifikací ve vestavěných systémech

Type

conference paper

Language

English

Authors

Švéda Miroslav, prof. Ing., CSc. (UTKO)

Keywords

Embedded systems, design systems, formal specification, computer communication networks, sensor systems

Abstract

This paper deals with reuse of architectural and behavioral specifications of embedded systems employing finite-state and timed automata. The contribution proposes not only how to represent a system’s formal specification as an application pattern structure of specification fragments, but also how to measure similarity of formal specifications for retrieval with case-based reasoning support. The paper provides also an insight into case-based reasoning support as applied to formal specification reuse by application patterns built on finite-state and timed automata. Those application patterns create a base for a pattern language supporting reuse-oriented design process for a class of real-time embedded systems. Copyright Š 2006 IFAC

Published

2006

Pages

78–83

Proceedings

Proceedings of IFAC Workshop on PROGRAMMABLE DEVICES and EMBEDDED SYSTEMS PDeS 2006

ISBN

80-214-3130-X

Publisher

Faculty of Electrical Engineering and Communication BUT

Place

Brno

BibTeX

@inproceedings{BUT22176,
  author="Miroslav {Švéda}",
  title="REUSE OF FORMAL SPECIFICATIONS IN EMBEDDED SYSTEMS DESIGN",
  booktitle="Proceedings of IFAC Workshop on PROGRAMMABLE DEVICES and EMBEDDED SYSTEMS PDeS 2006",
  year="2006",
  pages="78--83",
  publisher="Faculty of Electrical Engineering and Communication BUT",
  address="Brno",
  isbn="80-214-3130-X"
}