Publication Details

Methodology of Selecting Scan-Based Testability Improving Technique

KOTÁSEK, Z.; STRNADEL, J.; PEČENKA, T. Methodology of Selecting Scan-Based Testability Improving Technique. Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. p. 186-189. ISBN: 963-9364-48-7.
Czech title
Methodology of Selecting Scan-Based Testability Improving Technique
Type
conference paper
Language
English
Authors
Kotásek Zdeněk, doc. Ing., CSc.
Strnadel Josef, Ing., Ph.D. (DCSY)
Pečenka Tomáš, Ing., Ph.D.
URL
Keywords

design for testability, scan method, testable core

Abstract

In the paper, the solution of the problem of selecting the most optimal design-for-testability technique for register-transfer level digital circuits is demonstrated. A decision-making process that is able to solve the problem over a set of scan-based techniques is presented in the paper. The process decides among following testability improving techniques: identification of testable cores, covering of feedback loops by minimum set of scan registers, selection of registers into scan chains to achieve high level of parallelism during the test application.

Published
2005
Pages
186–189
Proceedings
Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop
ISBN
963-9364-48-7
Publisher
University of West Hungary
Place
Sopron
BibTeX 
@inproceedings{BUT21466,
  author="Zdeněk {Kotásek} and Josef {Strnadel} and Tomáš {Pečenka}",
  title="Methodology of Selecting Scan-Based Testability Improving Technique",
  booktitle="Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop",
  year="2005",
  pages="186--189",
  publisher="University of West Hungary",
  address="Sopron",
  isbn="963-9364-48-7",
  url="http://www.fit.vutbr.cz/~pecenka/pubs/2005_ddecs_scan.pdf"
}
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