Publication Details

Web-Based Simulator of Superscalar RISC-V Processors

JAROŠ, J.; MAJER, M.; HORKÝ, J.; VÁVRA, J. Web-Based Simulator of Superscalar RISC-V Processors. 2024. p. 0-0.
Type
miscellaneous
Language
English
Authors
Jaroš Jiří, doc. Ing., Ph.D. (DCSY)
Majer Michal, Ing.
Horký Jakub, Ing.
Vávra Jan, Ing.
Abstract

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to  grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.

Published
2024
BibTeX 
@misc{BUT192198,
  author="Jiří {Jaroš} and Michal {Majer} and Jakub {Horký} and Jan {Vávra}",
  title="Web-Based Simulator of Superscalar RISC-V Processors",
  year="2024",
  url="https://www.fit.vut.cz/research/publication/13258/",
  note="miscellaneous"
}
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