Publication Details
Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis
Mrázek Vojtěch, Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
approximate computing, approximate arithmetic circuit, formal analysis,
constrained verification
A fundamental assumption for search-based circuit approximation methods is the
ability to massively and efficiently traverse the search space and evaluate
candidate solutions. For complex approximate circuits (adders and multipliers),
common error metrics, and error analysis approaches (SAT solving, BDD analysis),
we perform a detailed analysis to understand the behavior of the error analysis
methods under constrained resources, such as limited execution time. In addition,
we show that when evaluating the error of a candidate approximate circuit, it is
highly beneficial to reuse knowledge obtained during the evaluation of previous
circuit instances to reduce the total design time. When an adaptive search
strategy that drives the search towards promptly verifiable approximate circuits
is employed, the method can discover circuits that exhibit better trade-offs
between error and desired parameters (such as area) than the same method with
unconstrained verification resources and within the same overall time budget. For
16-bit and 20-bit approximate multipliers, it was possible to achieve a 75%
reduction in area when compared with the baseline method.
@inproceedings{BUT188464,
author="Zdeněk {Vašíček} and Vojtěch {Mrázek} and Lukáš {Sekanina}",
title="Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis",
booktitle="2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)",
year="2024",
pages="1--6",
publisher="Institute of Electrical and Electronics Engineers",
address="Valencia",
isbn="979-8-3503-4859-0"
}