Publication Details
Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery
Fault-Tolerant System Design, Electronic Design Automation, Redundancy Insertion,
Redundancy Allocation, Multiple-choice Knapsack Problem, FPGA, VHDL, t50
This paper presents and describes our design automation toolkit for automatic
synthesis of fault tolerant systems from unhardened systems. The toolkit is
composed of various parts and tools and its aim is to design its internal
algorithms in such way to be reusable among different HW description languages.
In this paper, VHDL description is used to present the possibilities of the
toolkit. The experimental part of the paper presents automatic synthesis of
a benchmark system into a limited chip area. The optimization goal was to
maximize the median time to failure (a.k.a. t50) parameter. The main part of the
experimental activities comprises incorporation of a partial dynamic
reconfiguration controller into the system design to recover the selected
component of the system. Two systems utilizing recovery with the usage of the
FPGA dynamic reconfiguration technique show promising results in terms of
reliability. The recovered system, in which the controller is apart of the FPGA
(e.g. in a different radiation-hardened chip), achieves by 70% better t50
parameter, compared to the system without recovery.
@inproceedings{BUT175799,
author="Jakub {Lojda} and Richard {Pánek} and Zdeněk {Kotásek}",
title="Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery",
booktitle="2021 IEEE East-West Design and Test Symposium, EWDTS 2021 - Proceedings",
year="2021",
pages="26--33",
publisher="Institute of Electrical and Electronics Engineers",
address="Batumi",
doi="10.1109/EWDTS52692.2021.9580996",
isbn="978-1-6654-4503-0",
url="https://www.fit.vut.cz/research/publication/12529/"
}