Publication Details

Accelerating Tests of Arithmetic Circuits Through On-FPGA Stimuli Generation and Their Reduction

LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; KOTÁSEK, Z. Accelerating Tests of Arithmetic Circuits Through On-FPGA Stimuli Generation and Their Reduction. In International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2021. Mauritius: Institute of Electrical and Electronics Engineers, 2021. p. 1628-1633. ISBN: 978-1-6654-1262-9.
Czech title
Urychlení testu aritmetických obvodů skrze generování stimulů přímo na FPGA a jejich redukci
Type
conference paper
Language
English
Authors
Lojda Jakub, Ing., Ph.D. (DCSY)
Podivínský Jakub, Ing., Ph.D. (UFYZ)
Čekan Ondřej, Ing., Ph.D. (UFYZ)
Kotásek Zdeněk, doc. Ing., CSc.
Keywords

Fault-tolerant System Design Evaluation, Fault Tolerance Property Estimation, Functional Verification, High-level Synthesis, Test Bed Generation

Abstract

This paper evaluates the possibility to accelerate fault tolerance evaluation of arithmetic circuits through reduced stimuli. In our research, we used a simplistic on-chip stimuli generator producing numbers in a row with a certain step (i.e. every nth number). The results are obtained through experimentation on a real HW Field Programmable Gate Array. The results confirm the hypothesis, that there might exist appropriate settings, for which the critical bit detection precision becomes only slightly worse but the reliability verification will accelerate significantly. Thus, the correct detection of critical bits in relation to step size is evaluated as certain steps provide significantly lower precision of the estimation than others. Our data show that the steps of sizes larger than 30 do not provide any further effective acceleration. In this paper, evaluations requiring error rate per fault injection are also considered. We also propose a novel stair chart to illustrate the measurement of the error rate per each fault. The results show that the size of the circuit had a minimal impact on the precision. General conclusion is that, by tuning the proper settings of the simplistic generator, significant acceleration of the evaluation can be achieved. The low area overhead of the reduced stimuli generator leaves the saved resources to the tested unit, which in the case of parallel evaluation further supports the acceleration.

Published
2021
Pages
1628–1633
Proceedings
International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2021
ISBN
978-1-6654-1262-9
Publisher
Institute of Electrical and Electronics Engineers
Place
Mauritius
DOI
10.1109/ICECCME52200.2021.9590967
EID Scopus
2-s2.0-85119407500
BibTeX 
@inproceedings{BUT175784,
  author="Jakub {Lojda} and Jakub {Podivínský} and Ondřej {Čekan} and Zdeněk {Kotásek}",
  title="Accelerating Tests of Arithmetic Circuits Through On-FPGA Stimuli Generation and Their Reduction",
  booktitle="International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2021",
  year="2021",
  pages="1628--1633",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Mauritius",
  doi="10.1109/ICECCME52200.2021.9590967",
  isbn="978-1-6654-1262-9",
  url="https://www.fit.vut.cz/research/publication/12504/"
}
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