Publication Details

Evolutionary Design of Synthetic RTL Benchmark Circuits

PEČENKA, T.; KOTÁSEK, Z.; SEKANINA, L.; STRNADEL, J. Evolutionary Design of Synthetic RTL Benchmark Circuits. Informal Digest of Papers, IEEE European Test Workshop 2004. Montpellier: IEEE Computer Society, 2004. p. 107-108. ISBN: 000000000.
Czech title
Evoluční návrh testovacích obvodů na úrovni RT
Type
conference paper
Language
English
Authors
Pečenka Tomáš, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Strnadel Josef, Ing., Ph.D. (DCSY)
URL
Keywords

RTL benchmark circuits, RTL testability analysis, evolutionary techniques

Abstract

In the paper it is demonstrated how evolutionary techniques can be used for the process of generating benchmark circuits covering a wide scale of testability properties. To calculate the value of fitness function the approach based on analytical evaluation of testability parameters is used. The solutions which cannot be synthesized by a design system are avoided from the process of developing a new generation of benchmark circuits. A number of circuits have been evolved with the required and predefined value of  controllability and observability. The output of the methodology developed and implemented is in the form of component VHDL code. The results are discussed and trends for the future research in this field are indicated.

Published
2004
Pages
107–108
Proceedings
Informal Digest of Papers, IEEE European Test Workshop 2004
ISBN
000000000
Publisher
IEEE Computer Society
Place
Montpellier
BibTeX 
@inproceedings{BUT17130,
  author="Tomáš {Pečenka} and Zdeněk {Kotásek} and Lukáš {Sekanina} and Josef {Strnadel}",
  title="Evolutionary Design of Synthetic RTL Benchmark Circuits",
  booktitle="Informal Digest of Papers, IEEE European Test Workshop 2004",
  year="2004",
  pages="107--108",
  publisher="IEEE Computer Society",
  address="Montpellier",
  isbn="000000000",
  url="http://www.fit.vutbr.cz/~kotasek/pub/ets_04.pdf"
}
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