Publication Details
Synthesis of approximate circuits for LUT-based FPGAs
approximate circuits, logic synthesis, LUT
Approximate computing is an emerging paradigm that trades the accuracy of
computation to achieve gain in terms of design area, critical path delay and/or
power consumption. There is a rich body of literature showing that the
approximate hardware components serving as basic building blocks for
energy-efficient implementation of complex systems offer a remarkable gain in
efficiency and/or performance in exchange for small losses in output quality.
However, recent studies revealed that the approximate components optimized mainly
for ASICs offer asymmetric gain when used in FPGAs. In this work, we present an
iterative design method for automated synthesis of elementary approximate
components natively optimized for usage in LUT-based FPGAs. The method takes into
account the number of LUTs and LUT-level propagation delay instead of the number
of gates and logic levels typically considered in other works. Using this method,
we synthesized various approximate adders (up to 64-bit) and multipliers (8-bit
and 16-bit). Compared to the current state-of-the-art, our designs achieve better
trade-off when considered the worst case absolute error, number of LUTs and
propagation delay. The discovered approximate adders and multipliers are
available online in the form of Verilog netlists consisting of 4, 5 and 6-input
LUTs.
@inproceedings{BUT169184,
author="Zdeněk {Vašíček}",
title="Synthesis of approximate circuits for LUT-based FPGAs",
booktitle="24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)",
year="2021",
pages="17--22",
publisher="IEEE Computer Society",
address="Vienna",
doi="10.1109/DDECS52668.2021.9417066",
isbn="978-1-6654-3595-6",
url="https://www.fit.vut.cz/research/publication/12453/"
}