Publication Details
A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress
MARCHISIO, A.
BUSSOLINO, B.
Mrázek Vojtěch, Ing., Ph.D. (DCSY)
MARTINA, M.
MASERA, G.
Shafique Muhammad (FIT)
Design Space Exploration, Hardware Accelerator, Capsule Networks, Convolutional Neural Networks, Training
The Capsule Networks (CapsNets) is an advanced form of Convolutional Neural Network (CNN), capable of learning spatial relations and being invariant to transformations. CapsNets requires complex matrix operations which current accelerators are not optimized for, concerning both training and inference passes. Current state-of-the-art simulators and design space exploration (DSE) tools for DNN hardware neglect the modeling of training operations, while requiring long exploration times that slow down the complete design flow. These impediments restrict the real-world applications of CapsNets (e.g., autonomous driving and robotics) as well as the further development of DNNs in life-long learning scenarios that require training on low-power embedded devices. Towards this, we present XploreDL , a novel framework to perform fast yet high-fidelity DSE for both inference and training accelerators, supporting both CNNs and CapsNets operations. XploreDL enables a resource-efficient DSE for accelerators, focusing on power, area, and latency, highlighting Pareto-optimal solutions which can be a green-lit to expedite the design flow. XploreDL can reach the same fidelity as ARM's SCALE-sim, while providing 600x speedup and having a 50x lower memory-footprint. Preliminary results with a deep CapsNet model on MNIST for training accelerators show promising Pareto-optimal architectures with up to 0.4 TOPS/squared-mm and 800 fJ/op efficiency. With inference accelerators for AlexNet the Pareto-optimal solutions reach up to 1.8 TOPS/squared-mm and 200 fJ/op efficiency.
@inproceedings{BUT168152,
author="COLUCCI, A. and MARCHISIO, A. and BUSSOLINO, B. and MRÁZEK, V. and MARTINA, M. and MASERA, G. and SHAFIQUE, M.",
title="A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress",
booktitle="2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)}",
year="2020",
pages="34--36",
publisher="Institute of Electrical and Electronics Engineers",
address="Singapore",
doi="10.1109/CODESISSS51650.2020.9244038",
isbn="978-1-7281-9198-0",
url="https://www.fit.vut.cz/research/publication/12420/"
}