Publication Details
ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems
Mrázek Vojtěch, Ing., Ph.D. (DCSY)
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Shafique Muhammad (FIT)
Approximate Computing, FPGA, ASIC, Adder, Multiplier, Arithmetic Units, Machine Learning
There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal for ASICs might not be pareto-optimal for FPGAs. In this work, we present the ApproxFPGAs methodology that uses machine learning models to reduce the exploration time for analyzing the state-of-the-art ASIC-based ACs to determine the set of pareto-optimal FPGA-based ACs. We also perform a case-study to illustrate the benefits obtained by deploying these pareto-optimal FPGA-ACs in a state-of-the-art automation framework to systematically generate pareto-optimal approximate accelerators that can be deployed in FPGA-based systems to achieve high performance or low-power consumption.
@inproceedings{BUT168121,
author="PRABAKARAN, B. and MRÁZEK, V. and VAŠÍČEK, Z. and SEKANINA, L. and SHAFIQUE, M.",
title="ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems",
booktitle="2020 57th ACM/IEEE Design Automation Conference (DAC)",
year="2020",
pages="1--6",
publisher="Institute of Electrical and Electronics Engineers",
address="San Francisco",
doi="10.1109/DAC18072.2020.9218533",
isbn="978-1-4503-6725-7",
url="https://arxiv.org/abs/2004.10502"
}