Publication Details
Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study
Lojda Jakub, Ing., Ph.D. (DCSY)
Podivínský Jakub, Ing., Ph.D. (UFYZ)
Kotásek Zdeněk, doc. Ing., CSc.
Fault-Tolerant, Partial Dynamic Reconfiguration Controller, Fault Tolerance Property Estimation, FT-EST
This paper deals with a reliability analysis of a reconfiguration controller which can be a component of a fault-tolerant control system. This controller is designed for an FPGA to be capable of using partial dynamic reconfiguration of the FPGA to mitigate potential faults in the FPGAs configuration memory. These faults, which are called SEUs, can be induced by radiation effects. Therefore, fault tolerance measurement or estimation is very important for designing circuits for critical environments. Thus, the reliability of the reconfiguration controller itself is significant; therefore the Fault Tolerance ESTimation (FT-EST) framework is used for reliability evaluation, which is procured by the discovery of a number of critical configuration bits. Two approaches are used and compared: evaluations of used LUT only, and evaluations of all configuration bits. We ascertained a 20x reduction in time consumption at the expense of a proportional decrease in the amount of critical configuration bits discovered. The obtained results are nearly equivalent.
@inproceedings{BUT168116,
author="Richard {Pánek} and Jakub {Lojda} and Jakub {Podivínský} and Zdeněk {Kotásek}",
title="Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study",
booktitle="2020 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) : proceedings of technical papers",
year="2020",
pages="121--124",
publisher="IEEE Computer Society",
address="Hsinchu",
doi="10.1109/VLSI-DAT49148.2020.9196269",
isbn="978-1-7281-6083-2",
url="https://www.fit.vut.cz/research/publication/12101/"
}