Publication Details
Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination
Čekan Ondřej, Ing., Ph.D. (UFYZ)
Krčma Martin, Ing., Ph.D. (UFYZ)
Burget Radek, doc. Ing., Ph.D. (DIFS)
Hruška Tomáš, prof. Ing., CSc. (DIFS)
Kotásek Zdeněk, doc. Ing., CSc.
Pareto frontier, processor optimization, ASIP
A processor forms the basis of almost most of today's electronic devices. In
embedded systems, the emphasis is put not only on high performance but also on
the small size and low power consumption. Application-specific instruction set
processors present a solution that may be optimized for specific applications by
different modifications of their parameters where the trade-offs among the
parameters may be represented by a Pareto frontier. In this paper, we propose
a novel method of Pareto frontier merging to allow the optimization of
a processor for a whole set of applications rather than a single one. We provide
an experimental evaluation of the method on a model of a RISC-V processor and we
show that the proposed method provides better approximation of the source Pareto
frontiers than the state-of-the-art methods.
@inproceedings{BUT162659,
author="Jakub {Podivínský} and Ondřej {Čekan} and Martin {Krčma} and Radek {Burget} and Tomáš {Hruška} and Zdeněk {Kotásek}",
title="Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination",
booktitle="2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)",
year="2020",
pages="1--4",
publisher="IEEE Circuits and Systems Society",
address="San José",
doi="10.1109/LASCAS45839.2020.9068954",
isbn="978-1-7281-3427-7",
url="https://www.fit.vut.cz/research/publication/12081/"
}