Publication Details

Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study

PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2019. p. 20-21. ISBN: 978-80-01-06607-2.
Czech title
Případová studie výpočtu průniku multidimenzionálních Pareto front v optimalizaci procesoru
Type
conference paper
Language
English
Authors
Podivínský Jakub, Ing., Ph.D. (UFYZ)
Čekan Ondřej, Ing., Ph.D. (UFYZ)
Krčma Martin, Ing., Ph.D. (UFYZ)
Burget Radek, doc. Ing., Ph.D. (DIFS)
Hruška Tomáš, prof. Ing., CSc. (DIFS)
Kotásek Zdeněk, doc. Ing., CSc.
URL
Keywords

Pareto optimization, Pareto frontier, processor optimization, ASIP.

Abstract

Almost every today's electronic devices are equipped with a processor. Different applications require and depend on different properties of a  processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using a general purpose processors has proved ineffective which led to growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized to specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. Such a tool was developed in our previous research. It is able to find a set of Pareto-optimal processor configurations for a  specific application which can be a significant help in a device design. The cost of the design process can be cut significantly when a  processor is used in multiple designs. The gal of this paper is to introduce a tool able to find a suitable processor configuration for multiple application by constructing a compromise Pareto-optimal frontier of a processor configurations. The paper describes this problem on a theoretical level as well as it introduces a practical implementation and experimental evaluation of constructing a compromise Pareto frontier of a processor configurations for a set of applications. The experiments are based on a parameterizable RISC-V processor.

Published
2019
Pages
20–21
Proceedings
Proceedings of the 7th Prague Embedded Systems Workshop
ISBN
978-80-01-06607-2
Publisher
Czech Technical University
Place
Roztoky u Prahy
BibTeX 
@inproceedings{BUT162466,
  author="Jakub {Podivínský} and Ondřej {Čekan} and Martin {Krčma} and Radek {Burget} and Tomáš {Hruška} and Zdeněk {Kotásek}",
  title="Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study",
  booktitle="Proceedings of the 7th Prague Embedded Systems Workshop",
  year="2019",
  pages="20--21",
  publisher="Czech Technical University",
  address="Roztoky u Prahy",
  isbn="978-80-01-06607-2",
  url="http://pesw.fit.cvut.cz/2019/PESW_2019.pdf"
}
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