Publication Details
Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Dobai Roland, Ing., Ph.D. (CM-SFE)
Sýs Marek (VUT)
Švenda Petr
randomness testing, evolvable hardware, FPGA
Randomness testing is an important procedure that bit streams, produced by
critical cryptographic primitives such as encryption functions and hash
functions, have to undergo. In this paper, a new hardware platform for randomness
testing is proposed. The platform exploits the principles of genetic programming,
which is a machine learning technique developed for automated program and circuit
design. The platform is capable of evolving efficient randomness distinguishers
directly on a chip. Each distinguisher is represented as a Boolean polynomial in
the Algebraic Normal Form. Randomness testing is conducted for bit streams that
are either stored in an on-chip memory or generated by a circuit placed on the
chip. The platform is developed with a Xilinx Zynq-7000 All Programmable System
on Chip which integrates a field programmable gate array with on-chip ARM
processors. The platform is evaluated in terms of the quality of randomness
testing, performance and resources utilization. With power budget less than 3 W,
the platform provides comparable randomness testing capabilities with the
standard testing batteries running on a personal computer.
@article{BUT161411,
author="Vojtěch {Mrázek} and Lukáš {Sekanina} and Roland {Dobai} and Marek {Sýs} and Petr {Švenda}",
title="Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques",
journal="IEEE Trans. on VLSI Systems.",
year="2019",
volume="27",
number="12",
pages="2734--2744",
doi="10.1109/TVLSI.2019.2923848",
issn="1063-8210",
url="https://www.fit.vut.cz/research/publication/11687/"
}