Publication Details
Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards
Podivínský Jakub, Ing., Ph.D. (UFYZ)
Lojda Jakub, Ing., Ph.D. (DCSY)
Pánek Richard, Ing., Ph.D. (DCSY)
Krčma Martin, Ing., Ph.D. (UFYZ)
Kotásek Zdeněk, doc. Ing., CSc.
Electronic Lock, Stepper Motor, FPGA, Fault Tolerance, Stimuli Generation, Reconfiguration.
This research paper presents the analysis of electronic smart locks and explores the influences of faults on its controller unit. Electronic smart locks often utilize stepper motor as an actuator. Stepper motors, however, need a controller, which is usually implemented in a processor. The aim of our research is to examine the consequences of failing controller processor. In our previous research, we developed a platform for fault tolerance testing with the ability to monitor the impacts on the mechanical part. We also developed a framework for accelerated testing of fault tolerance properties. The processor can be implemented in an FPGA (Field Programmable Gate Array) in order to be able to emulate HW faults inside the processor. In this paper, the concept of testing a smart lock is presented alongside with the first experimental results utilizing direct generation of invalid stimuli for the stepper motor. In our research, we found out, that random errors probably could not be used to unauthorized unlock, especially if the lock utilizes a mechanical gearbox. Deeper logic and knowledge of the correct sequence of steps used by the selected motor are needed to perform the attack to unlock the lock. On the other hand, random sequences could cause that the lock will not be locked by falsifying the lock request sequence. The second interesting fact is that x % of faults in the valid sequence give the same rotation angle as 100-x % of faults.
@inproceedings{BUT159970,
author="Ondřej {Čekan} and Jakub {Podivínský} and Jakub {Lojda} and Richard {Pánek} and Martin {Krčma} and Zdeněk {Kotásek}",
title="Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards",
booktitle="Proceedings of the 2019 22nd Euromicro Conference on Digital System Design",
year="2019",
pages="506--513",
publisher="Institute of Electrical and Electronics Engineers",
address="Kalithea",
doi="10.1109/DSD.2019.00079",
isbn="978-1-7281-2861-0",
url="https://www.fit.vut.cz/research/publication/11968/"
}