Publication Details

Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430

SZURMAN, K.; KOTÁSEK, Z. Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430. In 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019). Cluj-Napoca: IEEE Computer Society, 2019. p. 136-140. ISBN: 978-1-7281-0073-9.
Czech title
Za běhu rekonfigurovatelná architektura odolná proti poruchám pro soft-core procesor NEO430
Type
conference paper
Language
English
Authors
Szurman Karel, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.
Keywords

fault recovery, partial dynamic reconfiguration, state synchronization, soft-core
processor, neo430, SEU, transient fault, SRAM FPGA

Abstract

Reconfigurable fault tolerant (FT) architecture can be implemented into SRAM FPGA
by using combination of Partial Dynamic Reconfiguration (PDR) and Triple Modular
Redundancy (TMR). SRAM FPGAs are susceptible to Single Event Upsets (SEUs) which
are the most common transient faults induced by cosmic radiation. SEU mitigation
mechanism is required when SRAM FPGAs are integrated into safety-critical
systems. An essential requirement for these systems is often to remain
fail-operational and perform implemented functionality after the occurrence of
a fault. In our research, we proposed a run-time FT architecture based on
coarse-grained TMR with triplicated soft-core processor neo430, PDR for removing
all transient SEU faults and the state synchronization allowing smooth state
recovery from the inconsistent state when reconfiguration of failed processor
instance was finished into the state where all three processors operate
synchronously. This paper describes developed FT architecture and fault recovery
strategy performing all necessary steps run-time and without additional blocking
of the system functionality. The state synchronization for soft-core processor
neo430 architecture is described in detail. Moreover, the paper presents
developed PDR framework used for validation of proposed fault recovery strategy.

Published
2019
Pages
136–140
Proceedings
22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019)
ISBN
978-1-7281-0073-9
Publisher
IEEE Computer Society
Place
Cluj-Napoca
DOI
10.1109/DDECS.2019.8724636
UT WoS
000492839800003
EID Scopus
2-s2.0-85067568979
BibTeX 
@inproceedings{BUT156849,
  author="Karel {Szurman} and Zdeněk {Kotásek}",
  title="Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430",
  booktitle="22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019)",
  year="2019",
  pages="136--140",
  publisher="IEEE Computer Society",
  address="Cluj-Napoca",
  doi="10.1109/DDECS.2019.8724636",
  isbn="978-1-7281-0073-9",
  url="https://www.fit.vut.cz/research/publication/11905/"
}
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