Publication Details

Special Session: How Approximate Computing impacts Verification, Test and Reliability

SEKANINA, L.; VAŠÍČEK, Z.; BOSIO, A.; TRAIOLA, M.; RECH, P.; OLIVEIRA, D.; FERNANDES, F.; DI CARLO, S. Special Session: How Approximate Computing impacts Verification, Test and Reliability. 2018 IEEE 36th VLSI Test Symposium. San Francisco: IEEE Computer Society, 2018. p. 0-0. ISBN: 978-1-5386-3774-6.
Czech title
Speciální sekce: Jak aproximativní počítání ovlivňuje verifikaci, testování a spolehlivost
Type
abstract
Language
English
Authors
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
BOSIO, A.
TRAIOLA, M.
RECH, P.
OLIVEIRA, D.
FERNANDES, F.
DI CARLO, S.
Keywords

digital circuit, approximate computing, verification, test, reliability

Abstract

A new designparadigm -- approximate computing -- was established to investigate howcomputer systems can be made better -- more energy efficient, faster, andless complex -- by relaxing the requirement that they areexactly correct. The purpose of this special session is to introduce anddiscuss how approximate computing can and how impact the verification, the testand the reliability of digital circuits. The presentations of the specialsession will propose two views: (i): how theapproximate computing paradigm impacts the design and manufacturing flow ofintegrated circuits; (ii): how theverification, testing and reliability disciplines can be exploited in theapproximate computing paradigms.

Published
2018
Pages
1
Book
2018 IEEE 36th VLSI Test Symposium
Conference
IEEE VLSI Test Symposium 2018, San Francisco, US
ISBN
978-1-5386-3774-6
Publisher
IEEE Computer Society
Place
San Francisco
DOI
10.1109/VTS.2018.8368628
UT WoS
000435280400009
EID Scopus
2-s2.0-85048364082
BibTeX 
@misc{BUT155724,
  author="SEKANINA, L. and VAŠÍČEK, Z. and BOSIO, A. and TRAIOLA, M. and RECH, P. and OLIVEIRA, D. and FERNANDES, F. and DI CARLO, S.",
  title="Special Session: How Approximate Computing impacts Verification, Test and Reliability",
  booktitle="2018 IEEE 36th VLSI Test Symposium",
  year="2018",
  pages="1",
  publisher="IEEE Computer Society",
  address="San Francisco",
  doi="10.1109/VTS.2018.8368628",
  isbn="978-1-5386-3774-6",
  url="https://www.fit.vut.cz/research/publication/11726/",
  note="abstract"
}
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