Publication Details

Input and Output Generation for the Verification of ALU: a Use Case

ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. Input and Output Generation for the Verification of ALU: a Use Case. In Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018. Kazan: IEEE Computer Society, 2018. p. 331-336. ISBN: 978-1-5386-5710-2.
Czech title
Generování vstupů a výstupů pro verifikaci ALU
Type
conference paper
Language
English
Authors
Čekan Ondřej, Ing., Ph.D. (UFYZ)
Pánek Richard, Ing., Ph.D. (DCSY)
Kotásek Zdeněk, doc. Ing., CSc.
Keywords

Stimuli generation, arithmetic logic unit, probabilistic constrained grammar, functional verification

Abstract

The paper presents the approach to universal stimuli generation for an arithmetic-logic unit (ALU). It is not focused only on input data generation, but it is possible to generate also expected output in one stimulus. The process of generation is based on a probabilistic constrained grammar which is designed to universally describe stimuli for various circuits. This grammar is processed by our framework. The experiment in functional verification, which shows the quality of generated stimuli, is also presented.

Published
2018
Pages
331–336
Proceedings
Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018
ISBN
978-1-5386-5710-2
Publisher
IEEE Computer Society
Place
Kazan
DOI
10.1109/EWDTS.2018.8524641
UT WoS
000517795800024
EID Scopus
2-s2.0-85057963277
BibTeX 
@inproceedings{BUT155097,
  author="Ondřej {Čekan} and Richard {Pánek} and Zdeněk {Kotásek}",
  title="Input and Output Generation for the Verification of ALU: a Use Case",
  booktitle="Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018",
  year="2018",
  pages="331--336",
  publisher="IEEE Computer Society",
  address="Kazan",
  doi="10.1109/EWDTS.2018.8524641",
  isbn="978-1-5386-5710-2",
  url="https://www.fit.vut.cz/research/publication/11833/"
}
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