Publication Details
An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller
Lojda Jakub, Ing., Ph.D. (DCSY)
Kotásek Zdeněk, doc. Ing., CSc.
FPGA, Fault Tolerance, Robot Controller, VHDL, Fault Tolerance Evaluation.
Field Programmable Gate Arrays (FPGAs) are becoming more popular in various areas. Single Event Upsets (SEUs) are faults caused by a charged particle in the configuration memory of SRAM-based FPGAs. Such a charged particle can cause incorrect behavior in the whole system. This problem becomes greater if such a system operates in an environment with increased radiation (e.g. space applications). Lots of techniques to harden FPGAs against faults exist and new ones are under investigation. One such technique is called Triple Modular Redundancy (TMR). It is important to evaluate these techniques on a real system with a real FPGA. An evaluation platform based on an artificial fault injection and a functional verification for testing fault tolerance methodologies is introduced in this paper. Parts of our experimental system are hardened by using TMR and its experimental evaluation is one of the main parts of this paper. We propose experiments with various fault injection strategies (single and multiple faults) and monitor its impact on both the electronic and mechanical parts of the experimental system.
@inproceedings{BUT155060,
author="Jakub {Podivínský} and Jakub {Lojda} and Zdeněk {Kotásek}",
title="An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller",
booktitle="Proceedings of IEEE East-West Design & Test Symposium",
year="2018",
pages="63--69",
publisher="IEEE Computer Society",
address="Kazan",
doi="10.1109/EWDTS.2018.8524627",
isbn="978-1-5386-5710-2",
url="https://www.fit.vut.cz/research/publication/11747/"
}