Publication Details
Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis
Podivínský Jakub, Ing., Ph.D. (UFYZ)
Kotásek Zdeněk, doc. Ing., CSc.
High-Level Synthesis, Fault Tolerance Evaluation, Fault Tolerance Estimation
Framework, Catapult C, C++, VHDL.
During the last decades, electronic systems became an important matter of
controlling many critical processes. However, those critical processes often
require increased reliability. This requirement puts pressure on system
developers to make systems reliable. Because of ever growing chip-level
integration, capabilities of electronic systems are expanding, and, thus, leading
to more complex system architectures, significantly increasing the number of
man-hours needed to develop such systems. Many people believe the solution is to
move the development to a higher level of abstraction (e.g. an algorithm level)
and use the so-called High-Level Synthesis (HLS) for this purpose. In this
research, we aimed towards a decision, whether the usage of HLS impacts the
resulting reliability properties of the system, and, thus, whether the
HLS-generated system matches reliability properties of its corresponding
VHDL-implemented version. We found out that, for the selected set of circuits,
HLS performs better in terms of resource consumption, but, also, which we
consider surprising, in terms of reliability. For the selected set, HLS achieved
better reliability by 3.03 percentage points in contrast to the classical
approach utilizing a traditional Hardware Description Language (HDL). In these
experiments, no redundancy was intentionally inserted into benchmarking
circuits.
@inproceedings{BUT155010,
author="Jakub {Lojda} and Jakub {Podivínský} and Zdeněk {Kotásek}",
title="Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis",
booktitle="Proceedings of IEEE East-West Design & Test Symposium",
year="2018",
pages="80--86",
publisher="IEEE Computer Society",
address="Kazan",
doi="10.1109/EWDTS.2018.8524631",
isbn="978-1-5386-5710-2",
url="https://www.fit.vut.cz/research/publication/11752/"
}