Publication Details
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput
Benáček Pavel
Kekely Lukáš, Ing., Ph.D. (DCSY)
Kekely Michal, Ing., Ph.D.
Puš Viktor, Ing., Ph.D.
Kořenek Jan, doc. Ing., Ph.D. (DCSY)
packet parser, HLS, P4, Ethernet, high-speed networks, VHDL
As throughput of computer networks is on a constant rise, there is a need for ever-faster packet parsing modules at all points of the networking infrastructure. Parsing is a crucial operation which has an influence on the final throughput of a network device. Moreover, this operation must precede any kind of further traffic processing like filtering/classification, deep packet inspection, and so on. This paper presents a parser architecture which is capable to currently scale up to a terabit throughput in a single FPGA, while the overall processing speed is sustained even on the shortest frame lengths and for an arbitrary number of supported protocols. The architecture of our parser can be also automatically generated from a high-level description of a protocol stack in the P4 language which makes the rapid deployment of new protocols considerably easier. The results presented in the paper confirm that our automatically generated parsers are capable of reaching an effective throughput of over 1 Tbps (or more than 2000 Mpps) on the Xilinx UltraScale+ FPGAs and around 800 Gbps (or more than 1200 Mpps) on their previous generation Virtex-7 FPGAs.
@inproceedings{BUT146522,
author="Jakub {Cabal} and Pavel {Benáček} and Lukáš {Kekely} and Michal {Kekely} and Viktor {Puš} and Jan {Kořenek}",
title="Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput",
booktitle="Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays",
year="2018",
pages="249--258",
publisher="Association for Computing Machinery",
address="New York",
doi="10.1145/3174243.3174250",
isbn="978-1-4503-5614-5",
url="https://www.fit.vut.cz/research/publication/11674/"
}