State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture

fault tolerant system, FPGA, state synchronization,  partial dynamic reconfiguration, recovery, soft core processor.

Fault-tolerant systems implemented into SRAM-based FPGA are frequently protected by combination of triple modular redundancy and partial dynamic reconfiguration. When a part of the SRAM configuration memory with the copy of the protected circuit is reconfigured on the run, the system restart is the easiest way how to bring all three copies of the circuit back to fully synchronous and operating state. Soft core processors are complex systems which require more precise technique for synchronization of the system state space and data gained from previous calculations without disruption of processors functionality and executed program. This paper presents current state of our research focused on the state synchronization methodology for soft core processors.