Publication Details

Systémy odolné proti poruchám - metodika návrhu řadiče rekonfigurace

PÁNEK, R. Systémy odolné proti poruchám - metodika návrhu řadiče rekonfigurace. Počítačové architektury & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017. s. 24-27. ISBN: 978-80-972784-0-3.
English title
Fault Tolerant Systems - Reconfiguration controller design methodology
Type
conference paper
Language
Czech
Authors
Keywords

Reconfiguration controller, Fault Tolerant Systems, Partial Dynamic reconfiguration, FPGA

Abstract

The failures occurrences are very undesirable for not only critical control systems. Especially if it could lead to injury or financial loss. Therefore, techniques known as fault tolerant systems have been developed. Reconfiguration is especially useful for faults mitigation. The FPGA is an eligible reconfigured platform for designing and implementing circuits. A partial dynamic reconfiguration controller, which is a specially added component is highly beneficial to use for some FPGA circuit reparation by reconfiguration. Furthermore, it is desirable that the controller has fault tolerant, especially when it is placed in the same FPGA with desired circuit. The methodology, which will also be the topic of my dissertation will deal with this controller design and the developing of the relevant criteria.

Published
2017
Pages
24–27
Proceedings
Počítačové architektury & diagnostika 2017
ISBN
978-80-972784-0-3
Publisher
Slovenská technická univerzita v Bratislavě
Place
Smolenice
BibTeX
@inproceedings{BUT144458,
  author="Richard {Pánek}",
  title="Systémy odolné proti poruchám - metodika návrhu řadiče rekonfigurace",
  booktitle="Počítačové architektury & diagnostika 2017",
  year="2017",
  pages="24--27",
  publisher="Slovenská technická univerzita v Bratislavě",
  address="Smolenice",
  isbn="978-80-972784-0-3",
  url="https://www.fit.vut.cz/research/publication/11480/"
}
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