Publication Details

A multi-protocol cache controller

KUTÁLEK, V.; DVOŘÁK, V. A multi-protocol cache controller. IFAC Workshop on Programmable devices and systems - PDS 2003. Ostrava: VŠB - Technical University of Ostrava, 2003. p. 220-225. ISBN: 0-08-044130-0.
Czech title
Víceprotokolový řadič paměti cache
Type
conference paper
Language
English
Authors
Kutálek Vladimír, Ing., Ph.D.
Dvořák Václav, prof. Ing., DrSc.
Keywords

Cache coherence protocols, Bus multiprocessor systems, Tuning characteristics.

Abstract

Bus-based shared memory multiprocessors with per-processor caches use either invalidation or update protocols to maintain cache coherence. This paper suggests mixing protocols for different data objects within a single application, depending on whatever protocol is more efficient for an access pattern to a given object. The model of a two-protocol cache coherence controller has been created in CSP-based Transim language. Each cache line is tagged not only with the state, but also with the protocol type. Two most frequent 4-state, write-back protocols are implemented: MESI (invalidation) and Dragon (update) protocol. The model will be used for experimental evaluation of the proposed controller, which could then be used for processor cores with primary caches in SoC or for secondary caches in multiprocessors with standard microprocessors.

Published
2003
Pages
220–225
Proceedings
IFAC Workshop on Programmable devices and systems - PDS 2003
ISBN
0-08-044130-0
Publisher
VŠB - Technical University of Ostrava
Place
Ostrava
BibTeX
@inproceedings{BUT13782,
  author="Vladimír {Kutálek} and Václav {Dvořák}",
  title="A multi-protocol cache controller",
  booktitle="IFAC Workshop on Programmable devices and systems - PDS 2003",
  year="2003",
  pages="220--225",
  publisher="VŠB - Technical University of Ostrava",
  address="Ostrava",
  isbn="0-08-044130-0"
}
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