Publication Details

A Multi-protocol cache controller

KUTÁLEK, V.; DVOŘÁK, V. A Multi-protocol cache controller. IFAC Workshop on Programmable devices and systems - PDS 2003. Ostrava: VŠB - Technical University of Ostrava, 2003. p. 220-225. ISBN: 0-08-044130-0.

Czech title

Víceprotokolový řadič paměti cache

Type

conference paper

Language

English

Authors

Kutálek Vladimír, Ing., Ph.D.
Dvořák Václav, prof. Ing., DrSc.

Keywords

Cache coherence protocols, Bus multiprocessor systems, Tuning characteristics.

Abstract

Bus-based shared memory multiprocessors with per-processor caches useeither invalidation or update protocols to maintain cache coherence.This paper suggests mixing protocols for different data objects withina single application, depending on whatever protocol is more efficientfor an access pattern to a given object. The model of a two-protocolcache coherence controller has been created in CSP-based Transimlanguage. Each cache line is tagged not only with the state, but alsowith the protocol type. Two most frequent 4-state, write-back protocolsare implemented: MESI (invalidation) and Dragon (update) protocol. Themodel will be used for experimental evaluation of the proposedcontroller, which could then be used for processor cores with primarycaches in SoC or for secondary caches in multiprocessors with standardmicroprocessors.

Published

2003

Pages

220–225

Proceedings

IFAC Workshop on Programmable devices and systems - PDS 2003

ISBN

0-08-044130-0

Publisher

VŠB - Technical University of Ostrava

Place

Ostrava

BibTeX

@inproceedings{BUT13782,
  author="Vladimír {Kutálek} and Václav {Dvořák}",
  title="A Multi-protocol cache controller",
  booktitle="IFAC Workshop on Programmable devices and systems - PDS 2003",
  year="2003",
  pages="220--225",
  publisher="VŠB - Technical University of Ostrava",
  address="Ostrava",
  isbn="0-08-044130-0"
}