Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing

Seberekonfigurovatelný evolvable hardware systém pro adaptivní zpracování obrazu

journal article

English

Salvador Ruben (RG EHW)
Otero Andres
Mora Javier
De la Torre Eduardo
Riesgo Teresa
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)

evolutionary computing, genetic algorithms, evolvable hardware, FPGAs,
self-adaptive systems, reconfigurable hardware, adaptable architectures,
autonomous systems

This paper presents an evolvable hardware system, fully contained in an FPGA,
which is capable of autonomously generating digital processing circuits,
implemented on an array of processing elements (PEs). Candidate circuits are
generated by an embedded evolutionary algorithm and implemented by means of
dynamic partial reconfiguration, enabling evaluation in the final hardware. The
PE array follows a systolic approach, and PEs do not contain extra logic such as
path multiplexers or unused logic, so array performance is high. Hardware
evaluation in the target device and the fast reconfiguration engine used yield
smaller reconfiguration than evaluation times. This means that the complete
evaluation cycle is faster than software-based approaches and previous evolvable
digital systems. The selected application is digital image filtering and edge
detection. The evolved filters yield better quality than classic linear and
nonlinear filters using mean absolute error as standard comparison metric.
Results do not only show better circuit adaptation to different noise types and
intensities, but also a nondegrading filtering behavior. This means they may be
run iteratively to enhance filtering quality. These properties are even kept for
high noise levels (40 percent). The system as a whole is a step toward fully
autonomous, adaptive systems.

2013

1481–1493

IEEE TRANSACTIONS ON COMPUTERS, vol. 62, no. 8, ISSN 0018-9340

10.1109/TC.2013.78

000321221000002