Project Details

Hardware-Aware Machine Learning: From Automated Design to Innovative and Explainable Solutions

Project Period: 1. 1. 2024 – 31. 12. 2026

Project Type: grant

Code: GA24-10990S

Agency: Czech Science Foundation

Program: Standardní projekty

Czech title
Strojové učení zohledňující hardware: Od automatizovaného návrhu k inovativním a vysvětlitelným řešením
Type
grant
Keywords

evolutionary algorithm;approximate computing;deep neural network;machine learning;hardware accelerator;explainability;design automation;

Abstract

As machine learning (ML) technology penetrates embedded devices, a new class of design automation algorithms capable of generating hardware-aware implementations of ML algorithms is highly desired. In addition, a lot of effort is now invested in developing explainable ML. We hypothesize that the design time of hardware-aware implementations of ML systems showing additional properties (such as explainable behavior) can be substantially reduced if the used design automation algorithms employ suitable surrogate models for estimating the accuracy, hardware parameters, and other desired properties. In addition to developing suitable surrogate models, we will create a new method based on genetic programming for the automated design of highly-optimized ML models showing excellent trade-offs among the quality of service, hardware parameters, and explainability. The design method and ML models automatically generated by the method will be evaluated in case studies, including image classifiers, Parkinson's disease assessment, and command classifiers of brain signals.

Team members
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY) – research leader
Hurta Martin, Ing. (DCSY)
Malik Aamir Saeed, prof., Ph.D. (DCSY)
Mrázek Vojtěch, Ing., Ph.D. (DCSY)
Piňos Michal, Ing. (DCSY)
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Zaheer Muhammad Asad (DCSY)
Publications

2024

  • ARIF, M.; REHMAN, F.; SEKANINA, L.; MALIK, A. A comprehensive survey of evolutionary algorithms and metaheuristics in brain EEG-based applications. Journal of Neural Engineering, 2024, vol. 21, no. 5, p. 1-25. ISSN: 1741-2552. Detail
  • KLHŮFEK, J.; ŠAFÁŘ, M.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. In 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS). Kielce: Institute of Electrical and Electronics Engineers, 2024. p. 1-6. ISBN: 979-8-3503-5934-3. Detail
  • SEKANINA, L. Tutorial: Evolutionary Design Methods in Electronic Design Automation. IEEE 42nd International Conference on Computer Design (ICCD). Milano: IEEE Computer Society, 2024. p. 689-690. ISBN: 979-8-3503-8040-8. Detail
  • VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). Valencia: Institute of Electrical and Electronics Engineers, 2024. p. 1-6. ISBN: 979-8-3503-4859-0. Detail
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