Product Details
Tools for split RTL circuit into Testable blocks
Created: 2007
Czech title
Nástroje pro rozdělení obvodu na RT úrovni na Testovatelné bloky
Type
software
License
In order to use the result by another entity, it is always necessary to acquire a license
License Fee
The licensor does not require a license fee for the result
Authors
Herrman Tomáš, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.
Kotásek Zdeněk, doc. Ing., CSc.
Keywords
RTL, testability analysis, formal model, scan chain design, Testable block
Description
Developed tools make possible to split circuit written in formal model that was developed on DSC into Testable blocks and design scan chain. Outputs of tools are individual Testable blocks written in verilog.
Location
License Conditions
This product is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version, see http://www.fsf.org/licensing/licenses/gpl.html
Files
Projects
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, 2007-2013, running
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments