// Verilog definition of TB2
// created by TB

module TB2(N52, N53, N54, N55, N56, N57, N58, N59, N60, N61, N62, N63, N64);
input N52;
input N53;
input N54;
input N55;
input N56;
input N57;
input N58;
input N59;
output N60;
output N61;
output N62;
output N63;
output N64;

  wire N68;
  wire N69;

  dffs reg_Data_out_dup_6_r(N60, N52, N56, N68, N69);
  tri01 tri_Data_out_0(N55, N69, N64);
  mux21 ix285(N69, N54, N53, N60);
  tri01 tri_Data_out_1(N57, N69, N63);
  tri01 tri_Data_out_2(N58, N69, N62);
  tri01 tri_Data_out_3(N59, N69, N61);

endmodule
