// Verilog definition of TB4
// created by TB

module TB4(N72, N73, N74, N75, N76);
input N72;
input N73;
input N74;
output N75;
output N76;

  wire N77;
  wire N81;
  wire N82;
  wire N83;
  wire N85;

  dffr Q_0_EXMPLR(N77, N72, N73, N76, N81);
  dffr Q_1_EXMPLR_EXMPLR(N85, N72, N73, N75, N82);
  mux21 ix83(N82, N83, N74, N85);
  xor2 ix73(N76, N74, N77);
  xor2 ix102(N82, N76, N83);

endmodule
