// Verilog definition of TB1
// created by TB

module TB1(N37, N38, N39, N40, N41, N42, N43, N44);
input N37;
input N38;
input N39;
input N40;
input N41;
output N42;
output N43;
output N44;

  wire N48;
  wire N49;
  wire N51;
  wire N54;
  wire N58;
  wire N64;

  xor2 ix35(N38, N40, N44);
  xnor2 ix33(N48, N49, N43);
  mux21_ni ix25(N51, N38, N40, N54);
  inv02 ix107(N41, N51);
  xnor2_2x ix109(N37, N58, N49);
  xnor2_2x ix111(N41, N39, N58);
  xnor2 ix31(N41, N64, N42);
  mux21_ni ix29(N48, N58, N49, N64);
  buf02 ix118(N54, N48);

endmodule
