// Verilog definition of TB1
// created by TB

module TB1(N4, N5, N6, N7, N8, N9, N10, N11);
input N4;
input N5;
input N6;
input N7;
input N8;
output N9;
output N10;
output N11;

  wire N15;
  wire N16;
  wire N18;
  wire N21;
  wire N25;
  wire N31;

  xor2 ix35(N5, N7, N11);
  xnor2 ix33(N15, N16, N10);
  mux21_ni ix25(N18, N5, N7, N21);
  inv02 ix107(N8, N18);
  xnor2_2x ix109(N4, N25, N16);
  xnor2_2x ix111(N8, N6, N25);
  xnor2 ix31(N8, N31, N9);
  mux21_ni ix29(N15, N25, N16, N31);
  buf02 ix118(N21, N15);

endmodule
