// Verilog definition of TB1
// created by TB

module TB1(N6, N7, N8, N9, N10, N11, N12, N13);
input N6;
input N7;
input N8;
input N9;
input N10;
output N11;
output N12;
output N13;

  wire N17;
  wire N18;
  wire N20;
  wire N23;
  wire N27;
  wire N33;

  xor2 ix35(N7, N9, N13);
  xnor2 ix33(N17, N18, N12);
  mux21_ni ix25(N20, N7, N9, N23);
  inv02 ix107(N10, N20);
  xnor2_2x ix109(N6, N27, N18);
  xnor2_2x ix111(N10, N8, N27);
  xnor2 ix31(N10, N33, N11);
  mux21_ni ix29(N17, N27, N18, N33);
  buf02 ix118(N23, N17);

endmodule
