// Verilog definition of TB4
// created by TB

module TB4(N80, N81, N82, N83, N84, N85, N86, N87, N88, N89, N90, N91, N92);
input N80;
input N81;
input N82;
input N83;
input N84;
input N85;
input N86;
input N87;
output N88;
output N89;
output N90;
output N91;
output N92;

  wire N96;
  wire N97;

  dffs reg_Data_out_dup_6_r(N88, N80, N84, N96, N97);
  tri01 tri_Data_out_0(N83, N97, N92);
  mux21 ix285(N97, N82, N81, N88);
  tri01 tri_Data_out_1(N85, N97, N91);
  tri01 tri_Data_out_2(N86, N97, N90);
  tri01 tri_Data_out_3(N87, N97, N89);

endmodule
