// Verilog definition of TB1
// created by TB

module TB1(N10, N11, N12, N13, N14, N15, N16, N17);
input N10;
input N11;
input N12;
input N13;
input N14;
output N15;
output N16;
output N17;

  wire N21;
  wire N22;
  wire N24;
  wire N27;
  wire N31;
  wire N37;

  xor2 ix35(N11, N13, N17);
  xnor2 ix33(N21, N22, N16);
  mux21_ni ix25(N24, N11, N13, N27);
  inv02 ix107(N14, N24);
  xnor2_2x ix109(N10, N31, N22);
  xnor2_2x ix111(N14, N12, N31);
  xnor2 ix31(N14, N37, N15);
  mux21_ni ix29(N21, N31, N22, N37);
  buf02 ix118(N27, N21);

endmodule
