// Verilog definition of TB6
// created by TB

module TB6(N180, N181, N182, N183, N184, N185, N186, N187, N188, N189, N190, N191, N192);
input N180;
input N181;
input N182;
input N183;
input N184;
input N185;
input N186;
input N187;
output N188;
output N189;
output N190;
output N191;
output N192;

  wire N196;
  wire N197;

  dffs reg_Data_out_dup_6_r(N188, N180, N184, N196, N197);
  tri01 tri_Data_out_0(N183, N197, N192);
  mux21 ix285(N197, N182, N181, N188);
  tri01 tri_Data_out_1(N185, N197, N191);
  tri01 tri_Data_out_2(N186, N197, N190);
  tri01 tri_Data_out_3(N187, N197, N189);

endmodule
