// Verilog definition of TB1
// created by TB

module TB1(N5, N6, N7, N8, N9, N10, N11, N12);
input N5;
input N6;
input N7;
input N8;
input N9;
output N10;
output N11;
output N12;

  wire N16;
  wire N17;
  wire N19;
  wire N22;
  wire N26;
  wire N32;

  xor2 ix35(N6, N8, N12);
  xnor2 ix33(N16, N17, N11);
  mux21_ni ix25(N19, N6, N8, N22);
  inv02 ix107(N9, N19);
  xnor2_2x ix109(N5, N26, N17);
  xnor2_2x ix111(N9, N7, N26);
  xnor2 ix31(N9, N32, N10);
  mux21_ni ix29(N16, N26, N17, N32);
  buf02 ix118(N22, N16);

endmodule
