// Verilog definition of TB4
// created by TB

module TB4(N83, N84, N85, N86, N87, N88, N89, N90, N91, N92, N93, N94, N95);
input N83;
input N84;
input N85;
input N86;
input N87;
input N88;
input N89;
input N90;
output N91;
output N92;
output N93;
output N94;
output N95;

  wire N99;
  wire N100;

  dffs reg_Data_out_dup_6_r(N91, N83, N87, N99, N100);
  tri01 tri_Data_out_0(N86, N100, N95);
  mux21 ix285(N100, N85, N84, N91);
  tri01 tri_Data_out_1(N88, N100, N94);
  tri01 tri_Data_out_2(N89, N100, N93);
  tri01 tri_Data_out_3(N90, N100, N92);

endmodule
