// Verilog definition of TB1
// created by TB

module TB1(N12, N13, N14, N15, N16);
input N12;
input N13;
input N14;
output N15;
output N16;

  wire N17;
  wire N21;
  wire N22;
  wire N23;
  wire N25;

  dffr Q_0_EXMPLR(N17, N12, N13, N16, N21);
  dffr Q_1_EXMPLR_EXMPLR(N25, N12, N13, N15, N22);
  mux21 ix83(N22, N23, N14, N25);
  xor2 ix73(N16, N14, N17);
  xor2 ix102(N22, N16, N23);

endmodule
