// Verilog definition of TB2
// created by TB

module TB2(N36, N37, N38, N39, N40, N41, N42, N43, N44, N45, N46, N47, N48);
input N36;
input N37;
input N38;
input N39;
input N40;
input N41;
input N42;
input N43;
output N44;
output N45;
output N46;
output N47;
output N48;

  wire N52;
  wire N53;

  dffs reg_Data_out_dup_6_r(N44, N36, N40, N52, N53);
  tri01 tri_Data_out_0(N39, N53, N48);
  mux21 ix285(N53, N38, N37, N44);
  tri01 tri_Data_out_1(N41, N53, N47);
  tri01 tri_Data_out_2(N42, N53, N46);
  tri01 tri_Data_out_3(N43, N53, N45);

endmodule
