// Verilog
// created by TB

`include "m4b_register.v"
`include "m4b_1.v"
`include "m4b_2.v"
`include "m4b_3.v"
`include "m4b_4.v"

module m4b(PI_1, PI_2, PI_3, PI_4, PI_5, PI_6, PI_7, PI_8, PI_9, PI_10, PI_11, PI_12, CLK, PO_1, PO_2);
input PI_1;
input PI_2;
input PI_3;
input PI_4;
input PI_5;
input PI_6;
input PI_7;
input PI_8;
input PI_9;
input PI_10;
input PI_11;
input PI_12;
input CLK;
output PO_1;
output PO_2;

  TB1 iTB1(N4, N5, N6, N7, N8, N9, N10, N11);
  TB2 iTB2(N44, N45, N46, N47, N48, N49, N50);
  TB3 iTB3(N72, N73, N74, N75, N76, N77, N78, N79);
  TB4 iTB4(N112, N113, N114, N115, N116, N117, N118);
  dff r_1(CLK, N9, PO_1); // TB1, TB-1
  dff r_2(CLK, N10, PO_2); // TB1, TB-1
  dff r_3(CLK, N11, N44); // TB1, TB2
  dff r_4(CLK, N49, N4); // TB2, TB1
  dff r_5(CLK, N50, N5); // TB2, TB1
  dff r_6(CLK, N77, N6); // TB3, TB1
  dff r_7(CLK, N78, N7); // TB3, TB1
  dff r_8(CLK, N79, N8); // TB3, TB1
  dff r_9(CLK, N117, N45); // TB4, TB2
  dff r_10(CLK, N118, N46); // TB4, TB2
  dff r_11(CLK, PI_1, N47); // TB-1, TB2
  dff r_12(CLK, PI_2, N48); // TB-1, TB2
  dff r_13(CLK, PI_3, N72); // TB-1, TB3
  dff r_14(CLK, PI_4, N73); // TB-1, TB3
  dff r_15(CLK, PI_5, N74); // TB-1, TB3
  dff r_16(CLK, PI_6, N75); // TB-1, TB3
  dff r_17(CLK, PI_7, N76); // TB-1, TB3
  dff r_18(CLK, PI_8, N112); // TB-1, TB4
  dff r_19(CLK, PI_9, N113); // TB-1, TB4
  dff r_20(CLK, PI_10, N114); // TB-1, TB4
  dff r_21(CLK, PI_11, N115); // TB-1, TB4
  dff r_22(CLK, PI_12, N116); // TB-1, TB4

  wire N4;
  wire N5;
  wire N6;
  wire N7;
  wire N8;
  wire N9;
  wire N10;
  wire N11;
  wire N44;
  wire N45;
  wire N46;
  wire N47;
  wire N48;
  wire N49;
  wire N50;
  wire N72;
  wire N73;
  wire N74;
  wire N75;
  wire N76;
  wire N77;
  wire N78;
  wire N79;
  wire N112;
  wire N113;
  wire N114;
  wire N115;
  wire N116;
  wire N117;
  wire N118;

endmodule
