// Verilog definition of TB4
// created by TB

module TB4(N77, N78, N79, N80, N81);
input N77;
input N78;
input N79;
output N80;
output N81;

  wire N82;
  wire N86;
  wire N87;
  wire N88;
  wire N90;

  dffr Q_0_EXMPLR(N82, N77, N78, N81, N86);
  dffr Q_1_EXMPLR_EXMPLR(N90, N77, N78, N80, N87);
  mux21 ix83(N87, N88, N79, N90);
  xor2 ix73(N81, N79, N82);
  xor2 ix102(N87, N81, N88);

endmodule
