// Verilog definition of TB2
// created by TB

module TB2(N38, N39, N40, N41, N42, N43, N44, N45, N46, N47, N48, N49, N50);
input N38;
input N39;
input N40;
input N41;
input N42;
input N43;
input N44;
input N45;
output N46;
output N47;
output N48;
output N49;
output N50;

  wire N54;
  wire N55;

  dffs reg_Data_out_dup_6_r(N46, N38, N42, N54, N55);
  tri01 tri_Data_out_0(N41, N55, N50);
  mux21 ix285(N55, N40, N39, N46);
  tri01 tri_Data_out_1(N43, N55, N49);
  tri01 tri_Data_out_2(N44, N55, N48);
  tri01 tri_Data_out_3(N45, N55, N47);

endmodule
