// Verilog definition of TB2
// created by TB

module TB2(N62, N63, N64, N65, N66, N67, N68, N69, N70, N71, N72, N73, N74);
input N62;
input N63;
input N64;
input N65;
input N66;
input N67;
input N68;
input N69;
output N70;
output N71;
output N72;
output N73;
output N74;

  wire N78;
  wire N79;

  dffs reg_Data_out_dup_6_r(N70, N62, N66, N78, N79);
  tri01 tri_Data_out_0(N65, N79, N74);
  mux21 ix285(N79, N64, N63, N70);
  tri01 tri_Data_out_1(N67, N79, N73);
  tri01 tri_Data_out_2(N68, N79, N72);
  tri01 tri_Data_out_3(N69, N79, N71);

endmodule
