// Verilog definition of TB4
// created by TB

module TB4(N85, N86, N87, N88, N89);
input N85;
input N86;
input N87;
output N88;
output N89;

  wire N90;
  wire N94;
  wire N95;
  wire N96;
  wire N98;

  dffr Q_0_EXMPLR(N90, N85, N86, N89, N94);
  dffr Q_1_EXMPLR_EXMPLR(N98, N85, N86, N88, N95);
  mux21 ix83(N95, N96, N87, N98);
  xor2 ix73(N89, N87, N90);
  xor2 ix102(N95, N89, N96);

endmodule
