// Verilog definition of TB1
// created by TB

module TB1(N15, N16, N17, N18, N19);
input N15;
input N16;
input N17;
output N18;
output N19;

  wire N20;
  wire N24;
  wire N25;
  wire N26;
  wire N28;

  dffr Q_0_EXMPLR(N20, N15, N16, N19, N24);
  dffr Q_1_EXMPLR_EXMPLR(N28, N15, N16, N18, N25);
  mux21 ix83(N25, N26, N17, N28);
  xor2 ix73(N19, N17, N20);
  xor2 ix102(N25, N19, N26);

endmodule
