// Verilog definition of TB2
// created by TB

module TB2(N35, N36, N37, N38, N39, N40, N41, N42, N43, N44, N45, N46, N47);
input N35;
input N36;
input N37;
input N38;
input N39;
input N40;
input N41;
input N42;
output N43;
output N44;
output N45;
output N46;
output N47;

  wire N51;
  wire N52;

  dffs reg_Data_out_dup_6_r(N43, N35, N39, N51, N52);
  tri01 tri_Data_out_0(N38, N52, N47);
  mux21 ix285(N52, N37, N36, N43);
  tri01 tri_Data_out_1(N40, N52, N46);
  tri01 tri_Data_out_2(N41, N52, N45);
  tri01 tri_Data_out_3(N42, N52, N44);

endmodule
