// Verilog definition of TB1
// created by TB

module TB1(N22, N23, N24, N25, N26, N27, N28, N29);
input N22;
input N23;
input N24;
input N25;
input N26;
output N27;
output N28;
output N29;

  wire N33;
  wire N34;
  wire N36;
  wire N39;
  wire N43;
  wire N49;

  xor2 ix35(N23, N25, N29);
  xnor2 ix33(N33, N34, N28);
  mux21_ni ix25(N36, N23, N25, N39);
  inv02 ix107(N26, N36);
  xnor2_2x ix109(N22, N43, N34);
  xnor2_2x ix111(N26, N24, N43);
  xnor2 ix31(N26, N49, N27);
  mux21_ni ix29(N33, N43, N34, N49);
  buf02 ix118(N39, N33);

endmodule
