// Verilog definition of TB4
// created by TB

module TB4(N75, N76, N77, N78, N79);
input N75;
input N76;
input N77;
output N78;
output N79;

  wire N80;
  wire N84;
  wire N85;
  wire N86;
  wire N88;

  dffr Q_0_EXMPLR(N80, N75, N76, N79, N84);
  dffr Q_1_EXMPLR_EXMPLR(N88, N75, N76, N78, N85);
  mux21 ix83(N85, N86, N77, N88);
  xor2 ix73(N79, N77, N80);
  xor2 ix102(N85, N79, N86);

endmodule
