// Verilog definition of TB1
// created by TB

module TB1(N25, N26, N27, N28, N29);
input N25;
input N26;
input N27;
output N28;
output N29;

  wire N30;
  wire N34;
  wire N35;
  wire N36;
  wire N38;

  dffr Q_0_EXMPLR(N30, N25, N26, N29, N34);
  dffr Q_1_EXMPLR_EXMPLR(N38, N25, N26, N28, N35);
  mux21 ix83(N35, N36, N27, N38);
  xor2 ix73(N29, N27, N30);
  xor2 ix102(N35, N29, N36);

endmodule
