// Verilog definition of TB1
// created by TB

module TB1(N7, N8, N9, N10, N11, N12, N13, N14);
input N7;
input N8;
input N9;
input N10;
input N11;
output N12;
output N13;
output N14;

  wire N18;
  wire N19;
  wire N21;
  wire N24;
  wire N28;
  wire N34;

  xor2 ix35(N8, N10, N14);
  xnor2 ix33(N18, N19, N13);
  mux21_ni ix25(N21, N8, N10, N24);
  inv02 ix107(N11, N21);
  xnor2_2x ix109(N7, N28, N19);
  xnor2_2x ix111(N11, N9, N28);
  xnor2 ix31(N11, N34, N12);
  mux21_ni ix29(N18, N28, N19, N34);
  buf02 ix118(N24, N18);

endmodule
