// Verilog definition of TB1
// created by TB

module TB1(N17, N18, N19, N20, N21);
input N17;
input N18;
input N19;
output N20;
output N21;

  wire N22;
  wire N26;
  wire N27;
  wire N28;
  wire N30;

  dffr Q_0_EXMPLR(N22, N17, N18, N21, N26);
  dffr Q_1_EXMPLR_EXMPLR(N30, N17, N18, N20, N27);
  mux21 ix83(N27, N28, N19, N30);
  xor2 ix73(N21, N19, N22);
  xor2 ix102(N27, N21, N28);

endmodule
