// Verilog definition of TB1
// created by TB

module TB1(N7, N8, N9, N10, N11);
input N7;
input N8;
input N9;
output N10;
output N11;

  wire N12;
  wire N16;
  wire N17;
  wire N18;
  wire N20;

  dffr Q_0_EXMPLR(N12, N7, N8, N11, N16);
  dffr Q_1_EXMPLR_EXMPLR(N20, N7, N8, N10, N17);
  mux21 ix83(N17, N18, N9, N20);
  xor2 ix73(N11, N9, N12);
  xor2 ix102(N17, N11, N18);

endmodule
