// Verilog definition of TB4
// created by TB

module TB4(N67, N68, N69, N70, N71);
input N67;
input N68;
input N69;
output N70;
output N71;

  wire N72;
  wire N76;
  wire N77;
  wire N78;
  wire N80;

  dffr Q_0_EXMPLR(N72, N67, N68, N71, N76);
  dffr Q_1_EXMPLR_EXMPLR(N80, N67, N68, N70, N77);
  mux21 ix83(N77, N78, N69, N80);
  xor2 ix73(N71, N69, N72);
  xor2 ix102(N77, N71, N78);

endmodule
