// Verilog definition of TB4
// created by TB

module TB4(N81, N82, N83, N84, N85, N86, N87, N88, N89, N90, N91, N92, N93);
input N81;
input N82;
input N83;
input N84;
input N85;
input N86;
input N87;
input N88;
output N89;
output N90;
output N91;
output N92;
output N93;

  wire N97;
  wire N98;

  dffs reg_Data_out_dup_6_r(N89, N81, N85, N97, N98);
  tri01 tri_Data_out_0(N84, N98, N93);
  mux21 ix285(N98, N83, N82, N89);
  tri01 tri_Data_out_1(N86, N98, N92);
  tri01 tri_Data_out_2(N87, N98, N91);
  tri01 tri_Data_out_3(N88, N98, N90);

endmodule
