// Verilog definition of TB2
// created by TB

module TB2(N49, N50, N51, N52, N53, N54, N55, N56, N57, N58, N59, N60, N61);
input N49;
input N50;
input N51;
input N52;
input N53;
input N54;
input N55;
input N56;
output N57;
output N58;
output N59;
output N60;
output N61;

  wire N65;
  wire N66;

  dffs reg_Data_out_dup_6_r(N57, N49, N53, N65, N66);
  tri01 tri_Data_out_0(N52, N66, N61);
  mux21 ix285(N66, N51, N50, N57);
  tri01 tri_Data_out_1(N54, N66, N60);
  tri01 tri_Data_out_2(N55, N66, N59);
  tri01 tri_Data_out_3(N56, N66, N58);

endmodule
