// Verilog definition of TB1
// created by TB

module TB1(N12, N13, N14, N15, N16, N17, N18, N19);
input N12;
input N13;
input N14;
input N15;
input N16;
output N17;
output N18;
output N19;

  wire N23;
  wire N24;
  wire N26;
  wire N29;
  wire N33;
  wire N39;

  xor2 ix35(N13, N15, N19);
  xnor2 ix33(N23, N24, N18);
  mux21_ni ix25(N26, N13, N15, N29);
  inv02 ix107(N16, N26);
  xnor2_2x ix109(N12, N33, N24);
  xnor2_2x ix111(N16, N14, N33);
  xnor2 ix31(N16, N39, N17);
  mux21_ni ix29(N23, N33, N24, N39);
  buf02 ix118(N29, N23);

endmodule
