Course details

Advanced Digital Systems

PCS Acad. year 2024/2025 Winter semester 5 credits

This course is aimed at teaching advanced techniques of digital circuit design. Firstly, it presents a brief overview of basic approaches to modelling and simulation of digital circuits using the VHDL language and summarizes key properties of target technologies, such as ASIC and FPGA. Next, the course introduces advanced techniques of digital circuit design and synthesis (pipelining, retiming), which are supplemented by the application of constraints. The main part of the course is focused on modern approaches to the synthesis of digital circuits. This includes models and methods used for optimisation at the logical level and with respect to target technology, as well as approaches that build on synergy between the synthesis and verification of digital circuits. Apart from these main topics, the course is also focused on some additional topics, such as low-power design and the verification of digital circuits based on the OVM methodology.

Guarantor

Kořenek Jan, doc. Ing., Ph.D. (DCSY)

Course coordinator

Fučík Otto, doc. Dr. Ing. (DCSY)

Language of instruction

Czech

Completion

Examination (written)

Time span

  • 26 hrs lectures
  • 10 hrs pc labs
  • 16 hrs projects

Assessment points

  • 60 pts final exam (written part)
  • 18 pts mid-term test (written part)
  • 10 pts labs
  • 12 pts projects

Department

Department of Computer Systems (UPSY)

Lecturer

Kekely Lukáš, Ing., Ph.D. (DCSY)
Kořenek Jan, doc. Ing., Ph.D. (DCSY)
Matoušek Jiří, Ing., Ph.D. (DCSY)
Zachariášová Marcela, Ing., Ph.D. (DCSY)

Instructor

Kekely Lukáš, Ing., Ph.D. (DCSY)
Matoušek Jiří, Ing., Ph.D. (DCSY)
Zachariášová Marcela, Ing., Ph.D. (DCSY)

Learning objectives

To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.
The students are able to design complex constrained digital systems using contemporary design techniques and they know modern methods for synthesis and verification of these systems.

Prerequisite knowledge and skills

Digital system design, basic programming skills.

Study literature

  • Khatri S. P., Gulati K. (eds.): Advanced Techniques in Logic Synthesis, Optimizations and Applications, ISBN 978-1-4419-7517-1, 2011
  • Rabaey J., Pedram M.: Low Power Design Methodologies, Kluwer, ISBN 0792396308, 1996

Fundamental literature

  • M. Morris Mano, Michael D. Ciletti: Digital Design, ISBN  978-9353062019, 2018
  • Micheli G., High-Level Synthesis from Algorithm to Digital Circuit, ISBN 978-1-4020-8587-1, 2008

Syllabus of lectures

  • Combinatorial and sequential logic design techniques, algorithms, and tools review.
  • Review of digital design target technologies (ASIC, FPGA).
  • Advanced synthesis techniques (pipelining, retiming).
  • Constraint conditions.
  • Models and methods for modern synthesis of digital circuits (AIG, BDD, SAT solvers).
  • The modern synthesis of digital circuits (logic optimization).
  • Modern synthesis of digital circuits (optimization for target technology).
  • The synergy between synthesis and verification of digital circuits.
  • Low power design methodologies.
  • Development tools for FPGA and SoC.
  • Verification of digital circuits (OVM methodology).

Syllabus of computer exercises

  • Synthesis of the basic logic circuits, pipelining, retiming.
  • Constraint conditions.
  • Synthesis of basic digital circuits using ABC tool.
  • Synthesis of advanced digital circuits using ABC tool.
  • Verification of digital circuits.

Syllabus - others, projects and individual work of students

  • Individual project focused on synthesis of digital circuits.

Progress assessment

Written mid-term exam and project in due dates.

Presence in any form of instruction is not compulsory. An absence (and hence loss of points) can be compensated in the following ways: 

  1. presence in another laboratory group dealing with the same task. 
  2. showing a summary of results to the tutor at the next lab. 
  3. sending a short report (summarizing the results of the missed lab and answering the questions from the assignment) to the tutor, in 14 days after the missed lab.

How to contact the teacher

Consultation after the lecture or exercise, or at any other time after an email agreement.

Schedule

DayTypeWeeksRoomStartEndCapacityLect.grpGroupsInfo
Tue comp.lab *) 1., 2., 3. of lectures N203 N204 N205 12:0013:5020 1MIT 2MIT xx
Tue exam 2025-01-07 E104 14:0015:50 1. termín
Tue lecture 1., 2., 11., 12. of lectures E104 17:0018:5070 1MIT 2MIT NEMB xx Kořenek
Tue lecture 3., 5., 6., 7., 9., 13. of lectures E104 17:0018:5070 1MIT 2MIT NEMB xx Matoušek
Tue lecture 2024-10-08 E104 17:0018:5070 1MIT 2MIT NEMB xx Kekely
Tue lecture 2024-11-05 E104 17:0018:5070 1MIT 2MIT NEMB xx
Tue lecture 2024-11-19 E104 17:0018:5070 1MIT 2MIT NEMB xx Zachariášová
Wed exam 2025-01-29 E104 12:0013:50 2. termín
Thu exam 2025-02-06 E105 15:0016:50 3. termín
Fri comp.lab *) 1., 2. of lectures N103 N104 N105 16:0017:5020 1MIT 2MIT xx
It is not possible to register this class in Studis. (Some exercises may be opened later if needed, but this is not guaranteed.)

Course inclusion in study plans

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