Course details

Advanced Digital Systems

PCS Acad. year 2017/2018 Winter semester 5 credits

Current academic year

Combinatorial and sequential logic design techniques, algorithms, and tools review. Review of digital design target technologies (ASIC, FPGA). Algorithms for minimization of digital circuits. Advanced synthesis techniques (pipelining, retiming). Constraint conditions. Modern approaches to synthesis of digital circuits (models, methods, logic optimization, optimization for target technology). Synergy of modern syntehesis and verification. Low power design methodologies. Reconfigurable computing. Verification of digital circuits (OVM methodology).

Guarantor

Fučík Otto, doc. Dr. Ing. (DCSY)

Language of instruction

Czech

Completion

Examination (written)

Time span

  • 26 hrs lectures
  • 10 hrs pc labs
  • 16 hrs projects

Assessment points

  • 60 pts final exam (written part)
  • 18 pts mid-term test (written part)
  • 10 pts labs
  • 12 pts projects

Department

Department of Computer Systems (UPSY)

Subject specific learning outcomes and competences

The students are able to design complex constrained digital systems using contemporary design techniques and they know modern methods for synthesis and verification of these systems.

Learning objectives

To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.

Prerequisite knowledge and skills

Digital system design, basic programming skills.

Study literature

  • Khatri S. P., Gulati K. (eds.): Advanced Techniques in Logic Synthesis, Optimizations and Applications, ISBN 978-1-4419-7517-1, 2011
  • Rabaey J., Pedram M.: Low Power Design Methodologies, Kluwer, ISBN 0792396308, 1996

Fundamental literature

  • Micheli G., High-Level Synthesis from Algorithm to Digital Circuit, ISBN 978-1-4020-8587-1, 2008

Syllabus of lectures

  • Combinatorial and sequential logic design techniques, algorithms, and tools review.
  • Review of digital design target technologies (ASIC, FPGA).
  • Algorithms for minimization of digital circuits.
  • Advanced synthesis techniques (pipelining, retiming).
  • Constraint conditions.
  • Models and methods for modern synthesis of digital circuits (AIG, BDD, SAT solvers).
  • Modern synthesis of digital circuits (logic optimization).
  • Modern synthesis of digital circuits (optimization for target technology).
  • Synergy between synthesis and verification of digital circuits.
  • Low power design methodologies.
  • Reconfigurable computing.
  • Verification of digital circuits (OVM methodology).

Syllabus of computer exercises

  • Synthesis of the basic logic circuits, pipelining, retiming.
  • Constraint conditions.
  • Synthesis of basic digital circuits using ABC tool.
  • Synthesis of advanced digital circuits using ABC tool.
  • Verification of digital circuits.

Progress assessment

Study evaluation is based on marks obtained for specified items. Minimimum number of marks to pass is 50.

Requirements for class accreditation are not defined.

Controlled instruction

Written mid-term exam and project in due dates.

Course inclusion in study plans

Back to top